JTAG Timing
10.14 JTAG Timing
Table 10-19 JTAG Timing
Characteristic
Symbol
Min
DC
50
5
Max
Unit
MHz
ns
See Figure
TCK frequency of operation1
TCK clock pulse width
fOP
SYS_CLK/8
10-16
10-16
10-17
10-17
10-17
10-17
tPW
tDS
tDH
tDV
tTS
—
—
—
30
30
TMS, TDI data set-up time
TMS, TDI data hold time
TCK low to TDO data valid
TCK low to TDO tri-state
ns
5
ns
—
—
ns
ns
1. TCK frequency of operation must be less than 1/8 the processor rate.
1/fOP
tPW
tPW
VIH
VM
VM
TCK
(Input)
VIL
VM = VIL + (VIH – VIL)/2
Figure 10-16 Test Clock Input Timing Diagram
TCK
(Input)
tDS
tDH
TDI
TMS
Input Data Valid
(Input)
tDV
TDO
(Output)
Output Data Valid
tTS
TDO
(Output)
Figure 10-17 Test Access Port Timing Diagram
56F8037/56F8027 Data Sheet, Rev. 6
Freescale Semiconductor
161
FREESCALE [ Freescale ]
