SS
(Input)
tF
tC
tR
tCL
SCLK (CPOL = 0)
(Input)
tCH
tELG
tELD
tCL
SCLK (CPOL = 1)
(Input)
tDV
tCH
tR
tD
tA
tF
MISO
Slave MSB out
MSB in
Bits 14–1
tDV
Slave LSB out
(Output)
tDS
tDI
tDH
MOSI
(Input)
Bits 14–1
LSB in
Figure 10-10 SPI Slave Timing (CPHA = 1)
10.10 Quad Timer Timing
1, 2
Table 10-15 Timer Timing
Characteristic
Timer input period
Symbol
PIN
Min
2T + 6
1T + 3
125
Max
—
Unit
ns
See Figure
10-11
Timer input high / low period
Timer output period
PINHL
POUT
—
ns
10-11
—
ns
10-11
Timer output high / low period
POUTHL
50
—
ns
10-11
1. In the formulas listed, T = the clock cycle. For 32MHz operation, T = 31.25ns.
2. Parameters listed are guaranteed by design.
56F8037/56F8027 Data Sheet, Rev. 6
156
FreescaleSemiconductor
FREESCALE [ Freescale ]
