56F8037 General Description
• Up to 32 MIPS at 32MHz core frequency
• Freescale’s scalable controller area network (MSCAN)
2.0 A/B Module
• DSP and MCU functionality in a unified,
C-efficient architecture
• Two 16-bit Quad Timers
2
• 64KB (32K x 16) Program Flash
• 8KB (4K x 16) Unified Data/Program RAM
• One 6-channel PWM module
• One Inter-Integrated Circuit (I C) port
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• Two 8-channel 12-bit Analog-to-Digital Converters
(ADCs)
• Integrated Power-On Reset (POR) and Low-Voltage
Interrupt (LVI) module
• Two 12-bit Digital-to-Analog Converters (DACs)
• Two Analog Comparators
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 53 GPIO lines
• 64-pin LQFP Package
• Three Programmable Interval Timers (PITs)
• Two Queued Serial Communication Interfaces (QSCIs)
with LIN slave functionality
• Two Queued Serial Peripheral Interfaces (QSPIs)
RESET or
GPIOA
V
2
V
3
V
V
V
SSA
CAP
DD
SS
DDA
4
4
JTAG/EOnCE
Port or
GPIOD
PWM
Digital Reg
Low-Voltage
Supervisor
Analog Reg
14
or TMRA or TMRB
or CMP or QSPI1
or GPIOA
16-Bit
56800E Core
Data ALU
Program Controller
and Hardware
Looping Unit
Address
Generation Unit
Bit
Manipulation
Unit
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
2
8
DAC
or GPIOD
PAB
PDB
CDBR
CDBW
AD0
Memory
ADC
R/W Control
or CMP
or QSCI1
or GPIOC
XDB2
XAB1
XAB2
Program Memory
32K x 16 Flash
8
System Bus
Control
AD1
PAB
Unified Data /
Program RAM
4K x 16
PDB
CDBR
CDBW
Programmable
Interval
Timer
IPBus Bridge (IPBB)
QSCI0
or PWM
2
QSPI0
I C
2
or PWM
or I C
or CAN
or TMRB
or CMP
2
or QSPI1
or TMRA
or TMRB
or GPIOB
or I C
XTAL, CLKIN, or
GPIOD
P
O
R
or TMRA
or GPIOB
System
Integration
Module
Interrupt
Controller
COP/
Watchdog
O
S
C
Clock
Generator*
or GPIOB
EXTAL or GPIOD
*Includes On-Chip
Relaxation Oscillator
6
4
4
56F8037 Block Diagram
56F8037 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
3
FREESCALE [ Freescale ]
