2
Table 10-18 I C Timing (Continued)
Standard Mode
Minimum Maximum
Fast Mode
Characteristic
Symbol
Unit
ns
Minimum
Maximum
5
Rise time of both SDA and
SCL signals
tr
tf
—
—
1000
300
—
300
20 +0.1Cb
5
Fall time of both SDA and
SCL signals
300
—
ns
20 +0.1Cb
Set-up time for STOP
condition
tSU; STO
4.0
4.7
0.6
μs
Bus free time between
STOP and START
condition
tBUF
—
1.3
0
—
μs
Pulse width of spikes that
must be suppressed by
the input filter
tSP
N/A
N/A
50
ns
2
1. The master mode I C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, a negative hold time can result, depending on the edge rates of the SDA and SCL lines.
2. The maximum t
must be met only if the device does not stretch the LOW period (t
) of the SCL signal.
HD; DAT
LOW
3. Set-up time in slave-transmitter mode is 1 iPBus clock period, if the TX FIFO is empty.
2
2
4. A Fast mode I C bus device can be used in a Standard mode I C bus system, but the requirement t
> = 250ns
SU; DAT
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
2
t
+ t
= 1000 + 250 = 1250ns (according to the Standard mode I C bus specification) before the SCL line is
rmax
SU; DAT
released.
5. C = total capacitance of the one bus line in pF
b
SDA
t
f
t
SU; DAT
t
t
t
t
t
t
SP
t
r
BUF
f
r
HD; STA
LOW
SCL
t
t
t
SU; STA
HD; STA
SU; STO
S
SR
P
S
t
t
HIGH
HD; DAT
2
Figure 10-15 Timing Definition for Fast and Standard Mode Devices on the I C Bus
56F8036 Data Sheet, Rev. 6
140
FreescaleSemiconductor
FREESCALE [ Freescale ]
