Reset, Stop, Wait, Mode Select, and Interrupt Timing
10.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Note:
All address and data buses described here are internal.
1,2
Table 10-13 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Characteristic
Symbol
tRA
Typical Min
Typical Max
Unit
ns
See Figure
Minimum RESET Assertion Duration
4T
—
—
10-6
—
Minimum GPIO pin Assertion for Interrupt
tIW
2T
96TOSC + 64T
—
—
97TOSC + 65T
6T
ns
RESET deassertion to First Address Fetch3
tRDA
tIF
ns
Delay from Interrupt Assertion to Fetch of first
instruction (exiting Stop)
ns
—
1. In the formulas, T = system clock cycle and T = oscillator clock cycle. For an operating frequency of 32MHz, T = 31.25ns. At
osc
8MHz (used during Reset and Stop modes), T = 125ns.
2. Parameters listed are guaranteed by design.
3. During Power-On Reset, it is possible to use the 56F8036 internal reset stretching circuitry to extend this period to 2^21T.
GPIO pin
(Input)
TIW
Figure 10-6 GPIO Interrupt Timing (Negative Edge-Sensitive)
56F8036 Data Sheet, Rev. 6
Freescale Semiconductor
133
FREESCALE [ Freescale ]
