Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F801 are organized into functional groups, as shown in Table 2-1
and as illustrated in Figure 2-1. In Table 2-2 through Table 2-12, each table row describes the signal or
signals present on a pin.
Table 2-1 Functional Group Pin Allocations
Number of
Pins
Detailed
Description
Functional Group
Power (VDD or VDDA
)
5
6
Table 2-2
Table 2-3
Ground (VSS or VSSA
)
Supply Capacitors
PLL and Clock
2
2
2
7
4
Table 2-4
Table 2-5
Table 2-6
Table 2-7
Table 2-8
Interrupt and Program Control
Pulse Width Modulator (PWM) Port
Serial Peripheral Interface (SPI) Port1
Serial Communications Interface (SCI) Port1
Analog-to-Digital Converter (ADC) Port
Quad Timer Module Port
2
Table 2-9
9
3
6
Table 2-10
Table 2-11
Table 2-12
JTAG/On-Chip Emulation (OnCE)
1. Alternately, GPIO pins
56F801 Technical Data, Rev. 17
8
Freescale Semiconductor
FREESCALE [ Freescale ]
