56F801 General Description
• Up to 30 MIPS operation at 60MHz core frequency
• Up to 40 MIPS operation at 80MHz core frequency
• 8K × 16-bit words (16KB) Program Flash
• 1K × 16-bit words (2KB) Program RAM
• 2K × 16-bit words (4KB) Data Flash
• 1K × 16-bit words (2KB) Data RAM
• 2K × 16-bit words (4KB) Boot Flash
• General Purpose Quad Timer
• JTAG/OnCETM port for debugging
• On-chip relaxation oscillator
• DSP and MCU functionality in a unified,
C-efficient architecture
• MCU-friendly instruction set supports both DSP and
controller functions: MAC, bit manipulation unit, 14
addressing modes
• Hardware DO and REP loops
• 6-channel PWM Module
• 11 shared GPIO
• Two 4-channel, 12-bit ADCs
• Serial Communications Interface (SCI)
• Serial Peripheral Interface (SPI)
• 48-pin LQFP Package
6
PWM Outputs
PWMA
RESET
Fault Input
VCAPC
2
V
V
V
V
SSA
DD
SS
DDA
IRQA
6
4
5*
Digital Reg
JTAG/
OnCE
Port
Analog Reg
Low Voltage
Supervisor
A/D1
A/D2
VREF
4
4
ADC
Interrupt
Controller
Data ALU
Address
Generation
Unit
Bit
Manipulation
Unit
Program Controller
and
Hardware Looping Unit
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Program Memory
8188 x 16 Flash
1024 x 16 SRAM
PAB
PLL
•
PDB
Quad Timer C
16-Bit
56800
Core
•
•
Clock Gen
or Optional
Internal
GPIOB3/XTAL
Quad Timer D
or GPIO
Boot Flash
2048 x 16 Flash
GPIOB2/EXTAL
3
XDB2
Relaxation Osc.
CGDB
Data Memory
2048 x 16 Flash
1024 x 16 SRAM
•
•
•
•
XAB1
XAB2
•
INTERRUPT
CONTROLS
IPBB
CONTROLS
16
SCI0
or
16
COP/
Watchdog
GPIO
2
4
COP RESET
MODULE CONTROLS
Applica-
tion-Specific
Memory &
Peripherals
IPBus Bridge
(IPBB)
SPI
or
GPIO
ADDRESS BUS [8:0]
DATA BUS [15:0]
*includes TCS pin which is reserved for factory use and is tied to VSS
56F801 Block Diagram
56F801 Technical Data, Rev. 17
Freescale Semiconductor
3
FREESCALE [ Freescale ]
