Data2 Valid
Data2
Data1 Valid
Data1
Data3 Valid
Data3
Data
Tri-stated
Data Invalid State
Data Active
Data Active
Figure 3-3 Signal States
3.4 Flash Memory Characteristics
Table 3-5 Flash Memory Truth Table
XE1
YE2
SE3
OE4
PROG5
ERASE6
MAS17
NVSTR8
Mode
Standby
Read
L
L
H
H
L
L
H
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
H
H
H
H
Word Program
Page Erase
Mass Erase
L
H
H
H
H
H
L
1. X address enable, all rows are disabled when XE = 0
2. Y address enable, YMUX is disabled when YE = 0
3. Sense amplifier enable
4. Output enable, tri-state Flash data out bus when OE = 0
5. Defines program cycle
6. Defines erase cycle
7. Defines mass erase cycle, erase whole block
8. Defines non-volatile store cycle
Table 3-6 IFREN Truth Table
Mode
IFREN = 1
IFREN = 0
Read
Read information block
Program information block
Erase information block
Erase both block
Read main memory block
Program main memory block
Erase main memory block
Erase main memory block
Word program
Page erase
Mass erase
56F801 Technical Data, Rev. 17
20
Freescale Semiconductor
FREESCALE [ Freescale ]
