Introduction
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56852 are organized into functional groups, as shown in
and
as illustrated in
In
each table row describes the package pin and the signal or
signals present.
Table 2-1 Functional Group Pin Allocations
Functional Group
Power (V
DD,
V
DDIO, or
V
DDA
)
Ground (V
SS,
V
SSIO,
or V
SSA
)
Phase Lock Loop (PLL) and Clock
External Bus Signals
External Chip Select*
Interrupt and Program Control
Synchronous Serial Interface (SSI) Port*
Serial Communications Interface (SCI) Port*
Serial Peripheral Interface (SPI) Port
Quad Timer Module Port
JTAG/Enhanced On-Chip Emulation (EOnCE)
*Alternately, GPIO pins
1. V
DD
= V
DD CORE,
V
SS
= V
SS CORE,
V
DDIO
= V
DD IO,
V
SSIO
= V
SS IO,
V
DDA
= V
DD ANA,
V
SSA
= V
SS ANA
2. CLKOUT is muxed Address pin A20.
3. Four Address pins are multiplexed with the timer, CS3 and CLKOUT pins.
4. CS3 is multiplexed with external Address Bus pin A19.
5. Mode pins are multiplexed with External Data pins D13-D15 like A17and A18.
6. Four of these pins are multiplexed with SSI.
7. Two of these pins are multiplexed with 2 bits of the External Address Bus A17and A18.
Number of Pins
10
1
10
1
2
2
39
3
3
4
3
5
6
2
0
6
0
7
6
56852 Technical Data, Rev. 8
Freescale Semiconductor
7
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
