ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
Tcs - SCLK
t
t
Tcs + SCLK
CS-SCLK
SCLK-CS
nCS
CS
Data latched on rising edge of SCLK
Data Latched on the rising edge of SCLK
SCLK
SCLK
t
t
DSU
Tdsu
DHD
Tend
SDI
SDI
Bit 1
Bit 1
Bit 2
Bit 2
Bit 3
Bit 3
Bit 4
Bit 4
Bit 5
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9 Bit 10 Bit 11 Bit 12 Bit 13
Bit 9 Bit 10 Bit 11 Bit 12 Bit 13*
Bit 6 Bit 7 Bit 8
SDI Stays at Last Value
LSB
LSB
MMSSBB
Time
Time
*SDI stays at last value
Figure 4. Serial Connectivity Diagram
Power On
“Glitch” Response
Power Off
Power Off
Power On
“Glitch” Response
VCC
Trip Level
Trip Level
VCC
Trip level
V
V
Trip level
V1T
V1T
VtVCC
ShSohrotrtggliltictchhbbeellooww V
V1T
VtVCC
for less than t
VtVCC for less than Tpersist
PERSIST
1.0 V
1 V
RESET
n RESET
undefined
Uunnddeefifnineded
Undefined
Tdelay 15-50mS
tDETLdeAlaYy 1155-5–05m0S ms
tDELAY 15–50 ms
tPERSIST
(plus Tpersist delay)
(plus Tpersist delay_
(plus tPERSIST
)
Tpersist delay
(plus tPERSIST
)
tPERSIST
Tpersist delay
Assumes VB+
> VtVB+
duri
>n
Vg the entire period
Figure 5. RESET Generation Timing Diagram (Assumes VVB+
During Entire Period)
VB+T+
34920
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
FREESCALE [ Freescale ]
