PIN CONNECTIONS
Table 2. 34704 Pin Definitions (continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on page 17.
Pin Number Device Pin Name Pin Function
Formal Name
Definition
47
48
49
50
51
52
53
REG2 Buck Stage
switching node
The inductor is connected between this pin and the SW2U pin.
A/B
A/B
A/B
A/B
A/B
A/B
A/B
SW2D
VOUT2
SW2U
SW5U
VOUT5
SW5D
PVIN5
Input/Output
Output
REG2 regulated output
voltage pin
Connect this pin to the load and to the output filter as close to
the pin as possible.
REG2 Boost Stage
switching node
The inductor is connected between this pin and the SW2D pin.
Input/Output
Input/Output
Output
REG5 Boost Stage
switching node
The inductor is connected between this pin and the SW5D pin.
REG5 regulated output
voltage pin
Connect this pin to the load and to the output filter as close to
the pin as possible.
REG5 Buck Stage
switching node
The inductor is connected between this pin and the SW5U pin.
Input/Output
Power
REG5 power supply input This is the connection to the drain of the high side switch FET.
voltage
Input decoupling /filtering is required for proper REG5 operation.
Use a 10uf decoupling capacitor for better performance
54
55
56
REG5 Buck Stage
Connect a 1.0 μF capacitor between this pin and SW5D pin to
A/B
A/B
BT5D
FB5
Passive
Input
bootstrap capacitor input enhance the gate of the Switch Power MOSFET.
pin
REG5 voltage feedback
input for voltage
regulation/programming
Connect the feedback resistor divider to this pin.
REG5 compensation network connection.
REG5 compensation
network connection
A/B
A/B
COMP5
PGND
Passive
Ground
Exposed
Pad
Power Ground
Connection for all of the
regulators except REG7
Power Ground Connection for all of the regulators except
REG7. This pad is provided to enhance thermal performance.
Notes
1. If regulator 1 is not used, leave pin 23 Unconnected, All other components should be used to provide VG to the system
2. If regulators 5, 6, 7 and 8 are not used, connect the corresponding pins as follows: FB node: tied to GND, BT node: Not connected, VOUT
node: Tied to GND, SW node: Tied to GND, DRV node: Tied to GND (REG7 only), COMP pin: Not connected, PVIN Pin: Not connected.
3. REG 2,3 and 4 should always be populated.
34704
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
FREESCALE [ Freescale ]
