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34704 参数 Datasheet PDF下载

34704图片预览
型号: 34704
PDF下载: 下载PDF文件 查看货源
内容描述: 多通道DC-DC电源管理IC [Multiple Channel DC-DC Power Management IC]
分类和应用:
文件页数/大小: 54 页 / 1389 K
品牌: FREESCALE [ Freescale ]
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FUNCTIONAL DEVICE OPERATION  
COMPONENT CALCULATION  
COMPONENT CALCULATION  
F
AND GENERAL SOFT START  
SW1  
CONFIGURATION  
Soft Start timing  
[ms]  
Ratio  
The 34704 uses FSW1 as the switching frequency for  
REG1(VG) thru REG5, and this can be changed by applying  
a voltage between 0 to 2.5 V to the FREQ pin. If the FREQ  
pin is left unconnected, the 34704 starts up with a default  
frequency of 750 KHz. To configure the FSW1, use a 2  
resistors voltage divider from VDDI to ground to set the  
voltage on the FREQ pin as indicated bellow:  
0
11/32  
0.5  
2.0  
19/32  
8.0  
VDDI  
32.0  
FSW1  
Ratio  
[KHz]  
I
DD max = 100μΑ  
0
750  
RSS2  
RSS1 + RSS2  
---------------------------------------  
VSS = VDDI  
VDDI  
9/32  
1000  
1250  
1500  
1750  
2000  
RSS1  
RSS1, RSS2 tolerance ±1.0%  
13/32  
17/32  
21/32  
VDDI  
V
SS  
SS  
RSS2  
GND  
REGULATORS POWER STAGE AND  
COMPENSATION CALCULATION  
Notes  
27. If an external voltage is used, FSW1 can only be set during  
device startup.  
Regulator 1 and 6 (Synchronous Boost - internally  
compensated - REG1 is VG supply).  
REG1 is a Synchronous Boost converter set to 5.0 V and  
Maximum current of 500 mA while REG6 is set to 15 V at  
60 mA (on the 34704B, REG1 does not exist but similar  
circuitry is used to provide the internal VG voltage). They do  
not need an external compensation network, thus, the only  
components that need to be calculated are:  
RF2  
RF1 + RF2  
-----------------------------  
VFREQ = VDDI  
VDDI  
RF1  
RF1, RF2 tolerance ±1.0%  
V
FREQ  
FREQ  
GND  
R1 and RB (Only REG6): These two resistors help to set  
the output voltage to the desire value using a Vref=0.6 V,  
select R1 between 10 k and 100 K and then calculate RB  
as follows:  
RF2  
Initially at power up, the soft start time will be set for all of  
the regulators through programming the SS pin with an  
external resistor divider connected between VDDI and AGND  
as follows:  
R1  
---------------------  
RB =  
[Ω]  
Vo  
-----------  
– 1  
Vref  
L: A boost power stage can be designed to operate in  
CCM for load currents above a certain level usually 5 to  
15% of full load. The minimum value of inductor to  
maintain CCM can be determined by using the following  
procedure:  
34704  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
39  
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