FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
Table 6. Regulator Analysis Table
REG1
REG2
REG3
REG4
REG5
REG6
REG7
REG8
Vin (V)
3.60
5.00
3.60
3.30
3.60
1.20
3.60
1.80
3.60
3.30
3.60
15
3.60
-7
3.60
15
Vout (V)
Iout_typ (A)
Iout_max (A)
DCR(mΩ)
Cout (μF)
0.100
0.500
230
0.200
0.500
230
0.150
0.550
230
0.100
0.300
310
0.150
0.500
230
0.050
0.060
230
0.050
0.060
230
0.015
0.030
230
22
22
22
22
22
22
22
22
ESR (mΩ)
Fsw (kHz)
Lout (μH)
9.00
9.00
9.00
9.00
9.00
9.00
9.00
9.00
1500
1.50
1500
1.50
1500
1.50
1500
1.50
1500
1.50
1000
4.70
1000
4.70
1000
4.70
Iin_typ (A)
Iin_max (A)
ILout_peak (A)
ICout_RMS (A)
Pout (W)
0.154
0.540
0.724
0.212
0.500
0.042
0.044
0.544
0.201
0.502
0.510
0.005
0.660
0.047
0.049
0.709
0.063
0.209
0.649
0.074
0.180
0.038
0.041
0.221
0.059
0.178
0.444
0.076
0.180
0.028
0.030
0.210
0.150
0.501
0.512
0.0006
0.495
0.034
0.035
0.530
0.254
0.304
0.444
0.071
0.750
0.135
0.145
0.895
0.107
0.128
0.443
0.129
0.350
0.000
0.027
0.377
0.077
0.154
0.297
0.043
0.225
0.045
0.047
0.272
Ploss On Chip (W)
Ploss Total (W)
Pin (W)
n (%)
91.90% 93.12% 81.48% 85.91% 93.33% 60.00% 69.00% 64.00%
Table 7. 34704A overall system efficiency 84%
Overall System
Table 8. 34704B overall system efficiency 89%
Overall System
Pout (W)
Pout (W)
3.340
0.369
0.41
1.74
0.192
0.202
1.942
89.6%
Ploss On Chip (W)
Ploss Total (W)
Pin (W)
Ploss On Chip (W)
Ploss Total (W)
Pin (W)
3.75
n (%)
n (%)
84.00%
34704
Analog Integrated Circuit Device Data
Freescale Semiconductor
26
FREESCALE [ Freescale ]
