ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
(Characteristics noted under conditions 4.75 V < VDD < 5.25 V, -40°C < TJ < 150°C, unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
SPI TIMING INTERFACE
Recommended Frequency of SPI Operation
f
—
—
—
—
—
—
—
—
—
—
—
1.0
50
50
25
25
25
25
—
—
—
—
3.0
167
167
83
MHz
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
SPI
Falling edge of CS to Rising Edge of SCLK (Required Setup Time)(15)
Falling edge of SCLK to Rising Edge of CS (Required Setup Time) (15)
SI to Falling Edge of SCLK (Required Setup Time) (15)
Falling Edge of SCLK to SI (Required Hold Time) (15)
SO Rise Time (CL=200pF)
T
LEAD
T
LAG
TS
LSU
TSI
83
(HOLD)
Tr
50
SO
SO
SO Fall Time (CL=200pF)
Tf
50
SI, CS, SCLK, Incoming Signal Rise Time (16)
Tr
50
SI
SI
SI, CS, SCLK, Incoming Signal Fall Time (16)
Tf
50
Falling Edge of RST to Rising Edge of RST (Required Setup Time)(15)
Tw
T
3.0
5.0
RST
14. Rising Edge of CS to Falling Edge of CS (Required Setup
Time)(15) (20)
CS
Rising Edge of RST to Falling Edge of CS (Required Setup Time)(15)
Time from Falling Edge of CS to SO Low Impedance (17)
Time from Rising Edge of CS to SO High Impedance (18)
Time from Rising Edge of SCLK to SO Data Valid (19)
T
—
—
—
—
—
—
5.0
145
4.0
µs
ns
µs
ns
EN
T
SO(EN)
SO(DIS)
T
1.3
65
T
105
VALID
0.2 V < = SO> = 0.8 V , CL = 200 pF
DD
DD
Notes
15. The maximum setup time that is specified for the 33991 is the minimum time needed from the micro controller to guarantee correct
operation.
16. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
17. Time required for output status data to be available for use at SO. 1 K Ohm load on SO
18. Time required for output status data to be terminated at SO. 1 K Ohm load on SO.
19. Time required to obtain valid data out from SO following the rise of SCLK.
20. This value is for a 1 MHz calibrated internal clock; it will change proportionally as the internal clock frequency changes.
The device shall meet all SPI interface-timing requirements specified in the SPI Interface Timing, over the temperature range
specified in the environmental requirements section. Digital Interface timing is based on a symmetrical 50% duty cycle SCLK
Clock Period of 333 ns. The device shall be fully functional for slower clock speeds.
33991
Analog Integrated Circuit Device Data
10
Freescale Semiconductor
FREESCALE [ Freescale ]
