ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SPI INTERFACE CHARACTERISTICS
Recommended Frequency of SPI Operation
fSPI
tWRST
tCS
–
–
–
–
–
–
–
–
–
–
–
50
–
3.0
350
300
5.0
167
167
167
167
83
MHz
ns
ns
μs
ns
ns
ns
ns
ns
ns
ns
(24)
Required Low State Duration for RST
Rising Edge of CS to Falling Edge of CS (Required Setup Time)(25)
Rising Edge of RST to Falling Edge of CS (Required Setup Time)(25)
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)(25)
Required High State Duration of SCLK (Required Setup Time)(25)
Required Low State Duration of SCLK (Required Setup Time)(25)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)(25)
SI to Falling Edge of SCLK (Required Setup Time)(26)
tENBL
tLEAD
tWSCLKh
tWSCLKl
tLAG
–
50
–
–
50
25
25
tSI(SU)
tSI(HOLD)
tRSO
Falling Edge of SCLK to SI (Required Setup Time)(26)
83
SO Rise Time
CL = 200 pF
–
25
50
SO Fall Time
CL = 200 pF
tFSO
ns
–
25
50
SI, CS, SCLK, Incoming Signal Rise Time(26)
tRSI
tRSI
–
–
–
–
–
–
50
50
ns
ns
ns
ns
ns
SI, CS, SCLK, Incoming Signal Fall Time(26)
Time from Falling Edge of CS to SO Low-impedance(27)
Time from Rising Edge of CS to SO High-impedance(28)
tSO(EN)
tSO(DIS)
tVALID
–
145
145
65
Time from Rising Edge of SCLK to SO Data Valid(29)
0.2 x VDD ≤ SO ≤ 0.8 x VDD, CL = 200 pF
–
65
105
Notes
24. RST low duration measured with outputs enabled and going to OFF or disabled condition.
25. Maximum setup time required for the 33984 is the minimum guaranteed time needed from the microcontroller.
26. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
27. Time required for output status data to be available for use at SO. 1.0 kΩ on pull-up on CS.
28. Time required for output status data to be terminated at SO. 1.0 kΩ on pull-up on CS.
29. Time required to obtain valid data out from SO following the rise of SCLK.
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
14
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