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33984 参数 Datasheet PDF下载

33984图片预览
型号: 33984
PDF下载: 下载PDF文件 查看货源
内容描述: 双智能大电流自我保护的硅的高边开关( 4.0毫欧) [Dual Intelligent High-current Self-protected Silicon High Side Switch (4.0 mOhm)]
分类和应用: 开关
文件页数/大小: 38 页 / 952 K
品牌: FREESCALE [ Freescale ]
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ELECTRICAL CHARACTERISTICS  
STATIC ELECTRICAL CHARACTERISTICS  
Table 4. Static Electrical Characteristics (continued)  
Characteristics noted under conditions 4.5 V VDD 5.5 V, 6.0 V VPWR 27 V, -40°C TA 125°C, unless otherwise noted.  
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
Control Interface  
Input Logic High Voltage(13)  
Input Logic Low Voltage(13)  
VIH  
VIL  
0.7 x VDD  
V
V
0.2 x  
VDD  
Input Logic Voltage Hysteresis(14)  
Input Logic Pull-down Current (SCLK, IN, SI)  
RST Input Voltage Range  
VIN[0:1](HYS)  
IDWN  
100  
5.0  
4.5  
600  
1200  
20  
mV  
μA  
V
VRST  
5.0  
5.5  
20  
SO, FS Tri-state Capacitance(15)  
Input Logic Pull-down Resistor (RST) and WAKE  
Input Capacitance(15)  
CSO  
pF  
kΩ  
pF  
V
RDWN  
100  
200  
4.0  
400  
12  
CIN  
WAKE Input Clamp Voltage(16)  
ICL(WAKE) < 2.5 mA  
VCL(WAKE)  
7.0  
-2.0  
14  
-0.3  
WAKE Input Forward Voltage  
ICL(WAKE) = -2.5 mA  
VF(WAKE)  
V
V
SO High-state Output Voltage  
IOH = 1.0 mA  
VSOH  
0.8x VDD  
FS, SO Low-state Output Voltage  
IOL = -1.6 mA  
VSOL  
V
0.2  
0
0.4  
5.0  
20  
SO Tri-state Leakage Current  
CS > 0.7VDD  
ISO(LEAK)  
μA  
μA  
kΩ  
-5.0  
Input Logic Pull-up Current(17)  
CS, VIN[0:1] > 0.7 x VDD  
IUP  
5.0  
FSI Input Pin External Pull-down Resistance  
FSI Disabled, HS[0:1] Indeterminate  
FSI Enabled, HS[0:1] OFF  
RFS  
RFSdis  
0
6.5  
1.0  
7.0  
19  
RFSoffoff  
RFSonoff  
RFSonon  
6.0  
15  
40  
FSI Enabled, HS0 ON, HS1 OFF  
FSI Enabled, HS[0:1] ON  
17  
Infinite  
Notes  
13. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN[0:1], and WAKE input signals. The WAKE and RST  
signals may be supplied by a derived voltage reference to VPWR  
.
14. No hysteresis on FSI and WAKE pins. Parameter is guaranteed by processing monitoring but is not production tested.  
15. Input capacitance of SI, CS, SCLK, RST, and WAKE. This parameter is guaranteed by process monitoring but is not production tested.  
16. The current must be limited by a series resistance when using voltages > 7.0 V.  
17. Pull-up current is with CS OPEN. CS has an active internal pull-up to VDD  
.
33984  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
11