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33981B 参数 Datasheet PDF下载

33981B图片预览
型号: 33981B
PDF下载: 下载PDF文件 查看货源
内容描述: 单高边开关( 4.0 mз ) , PWM时钟高达60kHz的 [Single High-Side Switch (4.0 mз), PWM clock up to 60kHz]
分类和应用: 开关时钟
文件页数/大小: 37 页 / 1043 K
品牌: FREESCALE [ Freescale ]
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FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
The 33981 has 2 operating modes: Sleep and Normal  
depending on EN input.  
NORMAL MODE  
The 33981 will go to the normal operating mode when the  
EN pin is logic [1]. The INHS and INLS commands will be  
disabled tON after the EN transitions to logic [1] to enable the  
charge of the bootstrap capacitor.  
SLEEP MODE  
Sleep mode is the state of the 33981 when the EN is  
logic [0]. In this mode, OUT, the gate driver for the external  
MOSFET, and all unused internal circuitry are off to minimize  
current draw.  
Table 5. Operating Modes  
Condition  
Sleep  
CONF INHS INLS OUT  
GLS  
x
FS  
H
EN  
Comments  
Device is in Sleep mode. The OUT and low-side gate are OFF.  
x
x
x
x
L
Normal mode. High side and low side are controlled  
Normal  
L
H
H
H
H
H
H
independently. The high side and the low side are both on.  
Normal mode. High side and low side are controlled  
independently. The high side and the low side are both off.  
Normal  
Normal  
Normal  
Normal  
L
L
L
L
L
H
L
L
L
L
H
L
H
H
H
H
H
H
H
H
Normal mode. Half-bridge configuration. The high side is off  
and the low side is on.  
Normal mode. Half-bridge configuration. The high side is on  
and the low side is off.  
L
H
H
Normal mode. Cross-conduction management is activated.  
Half-bridge configuration.  
H
PWM  
H
PWM PWM_bar  
H = High level  
L = Low level  
x = Don’t care  
PWM_bar = Opposite of pulse-width modulation signal.  
PROTECTION AND DIAGNOSTIC FEATURES  
offending load is removed. FS pin transition to logic [1] will be  
UNDERVOLTAGE  
disabled typically tON after to enable the charge of the  
bootstrap capacitor.  
The 33981 incorporates undervoltage protection. In case  
of VPWR<V  
(UV), the OUT is switched OFF until the power  
PWR  
Overtemperature faults force the TEMP pin to 0 V.  
supply rises to VPWR(UV)+VPWR(UVHYS). The latched fault are  
reset below V  
.
PWR(UV)  
OVERCURRENT FAULT ON HIGH SIDE  
OVERTEMPERATURE FAULT  
The OUT pin has an overcurrent high-detection level  
called IOCH for maximum device protection. If at any time the  
current reaches this level, OUT will stay OFF and the CSNS  
pin will go to 0 V. The OUT pin is reset (and the fault is  
The 33981 incorporates over temperature detection and  
shutdown circuitry on OUT. Overtemperature detection also  
protects the low-side gate driver (GLS pin). Overtemperature  
detection occurs when OUT is in the ON or OFF state and  
GLS is at high or low level.  
delatched) by a logic [0] at the INHS pin for at least tRST(diag)  
When INHS goes to 0 V, CSNS goes to 5.0 V.  
.
In Figure 16, page 19, the OUT pin is short-circuited to 0 V.  
When the current reaches IOCH, OUT is turned OFF within  
tOCH owing to internal logic circuit.  
For OUT, an over temperature fault condition results in  
OUT turning OFF until the temperature falls below TSD. This  
cycle will continue indefinitely until the offending load is  
removed. Figure 12, page 16 and Figure 18, page 20 show an  
over temperature on OUT.  
OVERLOAD FAULT ON LOW SIDE  
An over temperature fault on the low-side gate drive  
results in OUT turning OFF and the GLS going to 0 V until the  
temperature falls below TSD. This cycle will continue until the  
This fault detection is active when INLS is logic [1]. Low-  
side overload protection does not measure the current  
directly but rather its effects on the low-side MOSFET. When  
33981  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
13  
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