ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
CS
0.2 VDD
t
t
LEAD
LAG
0.7 VDD
0.2 VDD
SCLK
t
t
SI(SU) SI(HOLD)
0.7 VDD
0.2 VDD
SI
MSB in
t
t
VALID
SO(EN)
t
SO(DIS)
0.7 VDD
0.2 VDD
SO
MSB out
LSB out
Figure 4. SPI Timing Characteristics
VPWR
VDD
WAKE
INT
Wake-Up From Interrupt
Timer Expire
CS
Wake-Up From
Closed Switch
SGn
Power-Up
Normal Mode
Tri-State
Command
(Disable Tri-State)
Sleep
Command
Sleep Mode
Normal
Mode
Sleep Command
Sleep Mode
Normal
Mode
Sleep Command
Figure 5. Sleep Mode to Normal Mode Operation
Switch state change with
CS low generates INT
Switch state change with
CS low generates INT
INT
CS
Latch switch status
on falling edge of CS
Rising edge of CS does not
clear INT because state change
occurred while CS was low
SGn
Switch open “0”
Switch closed “1”
1
1
0
0
1
0
SGn Bit in SPI Word
Switch
Switch
Switch
Switch
Status
Switch
Status
Switch
Status
Status
Status
Status
Command
Command
Command
Command
Command
Command
Figure 6. Normal Mode Interrupt Operation
33975
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
FREESCALE [ Freescale ]
