FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33972 device is an integrated circuit designed to
provide systems with ultra-low quiescent sleep/wake-up
modes and a robust interface between switch contacts and a
microprocessor. The 33972 replaces many of the discrete
components required when interfacing to microprocessor-
based systems while providing switch ground offset
protection, contact wetting current, and system wake-up.
switch inputs may be read as analog inputs through the
analog multiplexer (AMUX). Other features include a
programmable wake-up timer, programmable interrupt timer,
programmable wake-up/interrupt bits, and programmable
wetting current settings.
This device is designed primarily for automotive
applications but may be used in a variety of other applications
such as computer, telecommunications, and industrial
controls.
The 33972 features 8-programmable switch-to-ground or
switch-to-battery inputs and 14 switch-to-ground inputs. All
FUNCTIONAL PIN DESCRIPTION
CHIP SELECT (CS)
SPI SLAVE IN (SI)
The system MCU selects the 33972 to receive
The SI pin is used for serial instruction data input. SI
information is latched into the input register on the falling
edge of SCLK. A logic HIGH state present on SI will program
a one in the command word on the rising edge of the CS
signal. To program a complete word, 24 bits of information
must be entered into the device.
communication using the chip select (CS) pin. With the CS in
a logic LOW state, command words may be sent to the 33972
via the serial input (SI) pin, and switch status information can
be received by the MCU via the serial output (SO) pin. The
falling edge of CS enables the SO output, latches the state of
the INT pin, and the state of the external switch inputs.
SPI SLAVE OUT (SO)
Rising edge of the CS initiates the following operation:
1. Disables the SO driver (high impedance)
The SO pin is the output from the shift register. The SO pin
remains tri-stated until the CS pin transitions to a logic LOW
state. All open switches are reported as zero, all closed
switches are reported as one. The negative transition of CS
enables the SO driver.
2. INT pin is reset to logic [1], except when additional
switch changes occur during CS LOW. (See Figure 6
on page 9.)
3. Activates the received command word, allowing the
33972 to act upon new data from switch inputs.
The first positive transition of SCLK will make the status
data bit 24 available on the SO pin. Each successive positive
clock will make the next status data bit available for the MCU
to read on the falling edge of SCLK. The SI/SO shifting of the
data follows a first-in, first-out protocol, with both input and
output words transferring the most significant bit (MSB) first.
To avoid any spurious data, it is essential the HIGH-to-
LOW and LOW-to-HIGH transitions of the CS signal occur
only when SCLK is in a logic LOW state. Internal to the 33972
device is an active pullup to VDD on CS.
In Sleep mode the negative edge of CS (VDD applied) will
wake up the 33972 device. Data received from the device
during CS wake-up may not be accurate.
iNTERRUPT (INT)
The INT pin is an interrupt output from the 33972 device.
The INT pin is an open-drain output with an internal pullup to
VDD. In Normal mode, a switch state change will trigger the
INT pin (when enabled). The INT pin and INT bit in the SPI
register are latched on the falling edge of CS. This permits the
MCU to determine the origin of the interrupt. When two 33972
devices are used, only the device initiating the interrupt will
have the INT bit set. The INT pin is cleared on the rising edge
of CS. The INT pin will not clear with rising edge of CS if a
switch contact change has occurred while CS was LOW.
SYSTEM CLOCK (SCLK)
The system clock (SCLK) pin clocks the internal shift
register of the 33972. The SI data is latched into the input
shift register on the falling edge of SCLK signal. The SO pin
shifts the switch status bits out on the rising edge of SCLK.
The SO data is available for the MCU to read on the falling
edge of SCLK. False clocking of the shift register must be
avoided to ensure validity of data. It is essential the SCLK pin
be in a logic LOW state whenever CS makes any transition.
For this reason, it is recommended, though not necessary,
that the SCLK pin is commanded to a logic LOW state as long
as the device is not accessed and CS is in a logic HIGH state.
When the CS is in a logic HIGH state, any signal on the SCLK
and SI pins will be ignored and the SO pin is tri-state.
In a multiple 33972 device system with WAKE HIGH and
VDD on (Sleep mode), the falling edge of INT will place all
33972s in Normal mode.
33972
Analog Integrated Circuit Device Data
Freescale Semiconductor
10
FREESCALE [ Freescale ]
