PIN CONNECTIONS
Table 1. 33926 Pin Definitions (continued)
A functional description of each pin can be found in the Functional Description section beginning on
page 12.
Pin
12, 13,
14, 15
16
18 – 20,
22 – 24
21
Pin Name
OUT1
D2
PGND
Pin
Function
Power
Output
Logic Input
Power
Ground
Logic
Output -
Open Drain
Logic Input
Power
Output
Analog
Output
Formal Name
H-Bridge Output 1
Disable Input 2
(Active Low)
Power Ground
Definition
Source of high-side MOSFET1 and drain of low-side MOSFET1.
When
D2
is logic LOW, both OUT1 and OUT2 are tri-stated. (Schmitt trigger
input with ~80
μA
sink so default condition = disabled.)
High-current power ground pins must be connected together physically as
close as possible and directly soldered down to a wide, thick, low resistance
ground plane on the PCB.
Open drain active LOW status flag output (requires an external pull-up resistor
to V
DD
. Maximum permissible load current < 0.5 mA. Maximum V
CEsat
< 0.4 V
@
0.3 mA. Maximum permissible pullup voltage < 7.0 V.)
When D1 is logic HIGH, both OUT1 and OUT2 are tri-stated. Schmitt trigger
input with ~80
μA
source so default condition = disabled.
Source of high-side MOSFET2 and drain of low-side MOSFET2.
External reservoir capacitor connection for internal charge pump; connected to
VPWR. Allowable values are 30 to 100
ηF.
Note: This capacitor is required for
the proper performance of the device.
SF
Status Flag
(Active Low)
Disable Input 1
(Active High)
H-Bridge Output 2
Charge Pump
Capacitor
26
27, 28,
29, 30
32
D1
OUT2
CCP
33926
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
