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33926 参数 Datasheet PDF下载

33926图片预览
型号: 33926
PDF下载: 下载PDF文件 查看货源
内容描述: 5.0油门控制H桥 [5.0 A Throttle Control H-Bridge]
分类和应用:
文件页数/大小: 25 页 / 599 K
品牌: FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
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PIN CONNECTIONS
PIN CONNECTIONS
VPWR
OUT2
OUT2
OUT2
OUT2
CCP
IN2
IN1
SLEW
1
2
3
4
5
6
7
8
9
32 31 30 29 28 27 26
D1
25
24
23
22
NC
PGND
PGND
PGND
SF
PGND
PGND
PGND
NC
Transparent Top
View of Package
VPWR
AGND
VPWR
INV
FB
NC
AGND
21
20
19
18
10 11 12 13 14 15 16
OUT1
OUT1
OUT1
VPWR
OUT1
EN
D2
17
Figure 3. 33926 Pin Connections
Table 1. 33926 Pin Definitions
A functional description of each pin can be found in the Functional Description section beginning on
Pin
1
Pin Name
IN2
Pin
Function
Logic Input
Formal Name
Input 2
Definition
Logic input control of OUT2; e.g., when IN2 is logic HIGH, OUT2 is set to V
PWR
,
and when IN2 is logic LOW, OUT2 is set to PGND. (Schmitt trigger input with
~ 80
μA
source so default condition = OUT2 HIGH.)
Logic input control of OUT1; e.g., when IN1 is logic HIGH, OUT1 is set to V
PWR
,
and when IN1 is logic LOW, OUT1 is set to PGND. (Schmitt trigger Input with
~ 80
μA
source so default condition = OUT1 HIGH.)
Logic input to select fast or slow slew rate. (Schmitt trigger input with ~ 80
μA
sink so default condition = slow.)
These pins must be connected together physically as close as possible and
directly soldered down to a wide, thick, low resistance supply plane on the PCB.
The low current analog signal ground must be connected to PGND via low
impedance path (<<10 mΩ, 0 Hz to 20 kHz). Exposed copper pad is also the
main heatsinking path for the device.
Sets IN1 and IN2 to logic LOW = TRUE. (Schmitt trigger input with ~ 80
μA
sink
so default condition = non-inverted.)
Load current feedback output provides ground referenced 0.24% of H-Bridge
high-side output current. (Tie pin to GND through a resistor if not used.)
No internal connection is made to this pin.
When EN is logic HIGH, the device is operational. When EN is logic LOW, the
device is placed in Sleep mode. (logic input with ~ 80
μA
sink so default
condition = Sleep mode.)
2
IN1
Logic Input
Input 1
3
4, 6, 11, 31
5,
Exposed
Pad
7
8
9, 17, 25
10
SLEW
VPWR
AGND
Logic Input
Power Input
Analog
Ground
Logic Input
Analog
Output
Slew Rate
Positive Power
Supply
Analog Signal
Ground
Input Invert
Feedback
No Connect
INV
FB
NC
EN
Logic Input
Enable Input
33926
Analog Integrated Circuit Device Data
Freescale Semiconductor
3