INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
V
V
PWR
DD
VIC
Internal
Regulator
Over/Undervoltage
Protection
I
I
UP
10 mΩ
CS
SCLK
Gate Driver
SPI
3.0 MHz
DWN
HS0
Selectable Current Limit
SO
SI
RST
WAKE
FS
Open Load
Detection
Overtemperature
Detection
Logic
HS0
IN0
IN1
IN2
Selectable Output Current
Recopy (Analog MUX)
CSNS0-1
HS1
IN3
ILS
Gate Control and Fault 10 mΩ
HS1
Gate Control and Fault 40 mΩ
HS2
HS2
R
I
DWN
DWN
Selectable Output Current
Recopy (Analog MUX)
CSNS2-3
Gate Control and Fault 40 mΩ
HS3
HS3
VIC
Watchdog
WDIN
FSI
Gate
Control
Clamp
LS4
LS5
LS6
LS7
LS8
LS9
LS10
LS11
Over-
temperature
I
LIM
Open Load
x 8
GND
Figure 2. 33888 Simplified Internal Block Diagram
33888
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
FREESCALE [ Freescale ]
