ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 17 V, -40°C ≤ TA ≤ 125°C unless otherwise
noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING
Output Rise Time (27)
Output Fall Time (27)
t
1.0
1.0
1.0
1.0
–
–
–
–
10
10
10
10
μs
μs
μs
μs
μs
R
t
F
Output Turn-ON Delay Time (28)
Output Turn-OFF Delay Time (29)
Output Short Fault Sense Time (30)
t
DLY(ON)
t
DLY(OFF)
t
SS
R
= < 1.0 V
25
–
100
LOAD
Output Short Fault Refresh Time (31)
= < 1.0 V
t
ms
REF
R
3.0
4.5
6.0
LOAD
Output OFF Open Load Sense Time (32)
Output ON Open Load Sense Time (33)
Output Short Fault ON Duty Cycle (34)
t
25
3.0
60
–
100
12
μs
ms
%
OS(OFF)
t
OS(ON)
SC
0.42
–
3.22
DC
DIGITAL INTERFACE TIMING
SCLK Clock High Time (SCLK = 3.2 MHz) (35)
SCLK Clock Low Time (SCLK = 3.2 MHz) (35)
Falling Edge (0.8 V) of CS to Rising Edge (2.0 V) of SCLK
Required Setup Time (35)
t
–
–
–
–
141
141
ns
ns
ns
SCLKH
SCLKL
t
t
LEAD
–
–
140
Falling Edge (0.8 V) of SCLK to Rising Edge (2.0 V) of CS
Required Setup Time (35)
t
ns
LAG
–
–
50
SI, CS, SCLK Incoming Signal Rise Time (35)
SI, CS, SCLK Incoming Signal Fall Time (35)
t
–
–
–
–
50
50
ns
ns
RSI
FSI
t
Notes
27. Output Rise and Fall time measured at 10% to 90% and 90% to 10% voltage points respectively across 15 Ω resistive load to a V
BAT
of 15 V, V
= 15 V.
PWR
28. Output Turn-ON Delay Time measured from rising edge (3.0 V) V (CS for serial) to 90% V using a 15 Ω load to a V of 15 V,
BAT
IN
O
V
= 15 V.
PWR
29. Output Turn-OFF Delay Time measured from falling edge (1.0 V) V (3.0 V rising edge of CS for serial) to 10% V using a 15 Ω load
IN
O
to a V
of 15 V, V
= 15 V.
BAT
PWR
30. The shorted output is turned ON during t to retry and check if the short has cleared. The shorted output is in current limit during t
.
SS
SS
The t is measured from the start of current limit to the end of current limit.
SS
31. The Short Fault Refresh Time is the waiting period between t retry signals. The shorted output is disabled during this refresh time.
SS
The t
is measured from the end of current limit to the start of current limit.
REF
32. The t
is measured from the time the faulted output is turned OFF until the fault bit is available to be loaded into the internal fault
OS(OFF)
register. To guarantee a fault is reported on SO, the falling edge of CS must occur at least 100 μs after the faulted output is off.
33. The t is measured from the time the faulted output is turned ON until the fault bit is available to be loaded into the internal fault
OS(ON)
register. To guarantee a fault is reported on SO, the falling edge of CS must occur at least 12 ms after the faulted output is ON.
34. Percent Output Short Fault ON Duty Cycle is defined as (t ) ÷ (t ) x 100. This specification item is provided FYI and is not tested.
SS
REF
35. Parameter is not tested and values suggested are for system design consideration only in preventing the occurrence of double pulsing.
33882
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
FREESCALE [ Freescale ]
