INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VDD
VPWR
VIC
Internal
Regulator
Over/Under-voltage
Protection
I
I
UP
CS
SCLK
VIC
Selectable Slew
Rate Gate Drive
SPI
3.0MHz
DWN
Selectable Over-current
High Detection
HS[0:3]: 55A or 40A
HS0
SO
SI
RST
WAKE
FS
Selectable Over-
current Low Detection
Blanking Time
Selectable Over-
current Low Detection
HS[0:3]: 2.8A–10A
Logic
IN0
0.15ms–155ms
IN1
IN2
IN3
Open Load
Detection
Over-temperature
Detection
HS0
R
I
DWN
DWN
HS1
HS1
HS2
HS3
VIC
Programmable
Watchdog
HS2
HS3
279ms–2250ms
FSI
Temperature
Feedback
Selectable Output Current
Recopy (Analog MUX)
TEMP
HS[0:3]: 1/7200 or 1/21400
GND
CSNS
Figure 2. 33874 Simplified Internal Block Diagram
33874
Analog Integrated Circuit Device Data
Freescale Semiconductor
2
FREESCALE [ Freescale ]
