ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 6.0V ≤ VPWR ≤ 27V, 4.5V ≤ VDD ≤ 5.5V, -40°C ≤ TA ≤ 125°C, GND = 0V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING (HS0, HS1, HS2, HS3) (continued)
Over-current High Detection Blanking Time
CS to CSNS Valid Time(24)
Watchdog Timeout(25)
WD[1:0] : 00
tOCH
1.0
–
5.0
–
20
10
μs
μs
tCNSVAL
ms
tWDTO0
tWDTO1
tWDTO2
tWDTO3
446
223
558
279
725
363
WD[1:0] : 01
WD[1:0] : 10
1800
900
2250
1125
2925
1463
WD[1:0] : 11
Direct Input Switching Frequency (DICR D3 = 0)
fPWM
-
300
-
Hz
SPI INTERFACE CHARACTERISTICS (RST, CS, SCLK, SI, SO)
Maximum Frequency of SPI Operation
fSPI
tWRST
tCS
–
–
–
–
–
–
–
–
–
–
–
50
–
3.0
350
300
5.0
167
167
167
167
83
MHz
ns
ns
μs
ns
ns
ns
ns
ns
ns
ns
(26)
Required Low-state Duration for RST
Rising Edge of CS to Falling Edge of CS (Required Setup Time)(27)
Rising Edge of RST to Falling Edge of CS (Required Setup Time)(27)
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)(27)
Required High-state Duration of SCLK (Required Setup Time)(27)
Required Low-state Duration of SCLK (Required Setup Time)(27)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)(27)
SI to Falling Edge of SCLK (Required Setup Time)(28)
Falling Edge of SCLK to SI (Required Setup Time)(28)
SO Rise Time
tENBL
–
tLEAD
tWSCLKh
tWSCLKl
tLAG
50
–
–
50
25
25
tSI(SU)
tSI(HOLD)
tRSO
83
C = 200pF
L
–
25
50
SO Fall Time
tFSO
ns
C = 200pF
L
SI, CS, SCLK, Incoming Signal Rise Time(28)
SI, CS, SCLK, Incoming Signal Fall Time(28)
Time from Falling Edge of CS to SO Low-impedance(29)
Time from Rising Edge of CS to SO High-impedance(30)
Time from Rising Edge of SCLK to SO Data Valid(31)
–
–
–
–
–
25
–
50
50
tRSI
tFSI
ns
ns
ns
ns
ns
–
50
tSO(EN)
tSO(DIS)
tVALID
–
145
145
65
0.2 V
≤ SO ≤ 0.8 x V , C = 200pF
–
65
105
DD
DD
L
Notes
24. Time necessary for the CSNS to be with ±5% of the targeted value.
25. Watchdog timeout delay measured from the rising edge of WAKE or RST from a sleep state condition, to output turn-ON with the output
driven OFF and FSI floating. The values shown are for WDR setting of [00]. The accuracy of t
is consistent for all configured
WDTO
watchdog timeouts.
26. RST low duration measured with outputs enabled and going to OFF or disabled condition.
27. Maximum setup time required for the 33874 is the minimum guaranteed time needed from the microcontroller.
28. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
29. Time required for output status data to be available for use at SO. 1.0kΩ on pull-up on CS.
30. Time required for output status data to be terminated at SO. 1.0kΩ on pull-up on CS.
31. Time required to obtain valid data out from SO following the rise of SCLK.
33874
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
FREESCALE [ Freescale ]
