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33811 参数 Datasheet PDF下载

33811图片预览
型号: 33811
PDF下载: 下载PDF文件 查看货源
内容描述: 螺线管​​显示器的集成电路(IC ) [Solenoid Monitor Integrated Circuit (IC)]
分类和应用: 显示器
文件页数/大小: 18 页 / 608 K
品牌: FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
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ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 10.5V
V
PWR
15.5V, - 40°C
T
A
125°C, GND = 0V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at T
A
= 25°C under nominal conditions, unless otherwise noted.
Characteristic
SPI DIGITAL INTERFACE TIMING
Required High State Duration on RESET for Reset to occur
t
RESET
Falling Edge of CS to Rising Edge of SCLK
Required Setup Time
Falling Edge of SCLK to Rising Edge of
CS
Required Setup Time
SI to Rising Edge of SCLK
Required Setup Time
Rising Edge of SCLK to SI
Required Hold Time
SI,
CS
, SCLK Signal Rise Time
SI,
CS
, SCLK Signal Fall Time
Time from Falling Edge of
CS
to SO Low-impedance
Time from Rising Edge of
CS
to SO High-impedance
Time from Falling Edge of SCLK to SO Data Valid
Sequential Transfer Rate
Time required between data transfers
Input Capacitance (SI, SCLK)
Load Capacitance (SO)
Tri-state Output Capacitance (SO)
WAVEFORM DETECTION TIMINGS
Start of Activation Filter Time
Detection Window Time
Sample Time
Notes:
10.
11.
12.
13.
14.
15.
16.
t
BEGIN
t
WINDOW
t
SAM
200
40
400
53
72
600
66
µs
ms
µs
C
INPUT
C
LOAD
C
TRI-STATE
7
15
200
20
pF
pF
pF
t
SI (HOLD)
t
R (SI)
t
F (SI)
t
SO (EN)
t
SO (DIS)
t
VALID
t
STR
20
5.0
5.0
65
65
80
55
90
1.0
ns
ns
ns
ns
ns
ns
µs
t
SI (SU)
16
ns
t
LAG
0
50
ns
t
LEAD
100
ns
1.0
µs
Symbol
Min
Typ
Max
Unit
These parameters are guaranteed by design. Production test equipment uses 3.2MHz, 5.0V SPI interface.
This parameter is guaranteed by design, however it is not production tested.
Rise and Fall time of incoming SI,
CS
, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for valid output status data to be available on SO pin.
Time required for output states data to be terminated at SO pin.
Time required to obtain valid data out from SO following the fall of SCLK with 200pF load.
9 µs guard band included in maximum limit
33811
8
Analog Integrated Circuit Device Data
Freescale Semiconductor