FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
the AND/OR register will AND the PWM input pin with the
respective bit in the ON/OFF register. The AND/OR function
is disabled when the PWM input pin is disabled.
Table 7. PWM Command
PWM Commands
Control Address
Command Bits
15
0
14
13
12
11
1
10
X
9
8
7
6
5
4
3
2
1
0
0
Rld Load Resistance
Measurement Select
Gate Drive ON/OFF Bit
GDX ON/OFF Command
0 = Off, 1 = On
1
0
0
0
0
0
0
0
0
0
0
0
PWM Controller
Enable Bit
PWM Pin Enable Bit
PWM Pin Enable Command
0 = PWMX Pin Enabled
1 = PWMX Pin Disabled
0
0
1
1
0
0
1
1
0
1
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PWM3 PWM2 PWM1
AND/OR Command
0
0
0
0 = PWMX Pin OR with SPI
1 = PWMX Pin AND with SPI
PWM6 PWM5 PWM4
Command
PWM1 Freq & DC
PWM2 Freq & DC
PWM3 Freq & DC
PWM4 Freq & DC
PWM5 Freq & DC
PWM6 Freq & DC
Control Address
Frequency Select
Duty Cycle Select
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
1
0
1
0
1
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Control Address
V DSNS3
VDSNS2
VDSNS1
VDSNS123 Short Threshold
VDSNS123 Short Timer
1
1
0
0
0
0
1
1
0
1
X
X
X
X
0
0
1
1
1
0
0
1
1
1
0
0
1
1
1
1
1
1
Control Address
VDSNS6
VDSNS5
VDSNS4
VDSNS456 Short Threshold
VDSNS456 Short Timer
1
1
0
0
1
1
0
0
0
1
X
X
X
X
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
Next SO Response (Message 1)
0 = No Fault, 1 = Fault
OvrVlt Reset Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault
,TLim
or
Statu Statu Statu Statu Statu Statu Statu Statu Statu Statu Statu Statu Statu Statu
sPW sPW sPW sPW sPW sPW sOUT sOUT sOUT sOUT sOUT sOUT sOUT sOUT
CAL
Flt
M6
M5
M4
M3
M2
M1
8
7
6
5
4
3
2
1
33800
Analog Integrated Circuit Device Data
Freescale Semiconductor
22
FREESCALE [ Freescale ]
