Ethernet: Three-Speed Ethernet, MII Management
8.2.3.1
TBI Transmit AC Timing Specifications
Table 29 provides the TBI transmit AC timing specifications.
Table 29. TBI Transmit AC Timing Specifications
At recommended operating conditions with LVDD/OVDD of 3.3 V 10%.
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
GTX_CLK clock period
tTTX
tTTXH/tTTX
tTTKHDX
tTTXR
—
40
1.0
—
8.0
—
—
—
—
—
60
ns
%
GTX_CLK duty cycle
GTX_CLK to TBI data TXD[7:0], TX_ER, TX_EN delay
GTX_CLK clock rise (20%–80%)
GTX_CLK clock fall time (80%–20%)
Notes:
5.0
1.0
1.0
ns
ns
ns
tTTXF
—
1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTTKHDV symbolizes the TBI transmit
timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the valid state (V)
or setup time. Also, tTTKHDX symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high (H) until
the referenced data signals (D) reach the invalid state (X) or hold time. In general, the clock reference symbol is based on
three letters representing the clock of a particular function. For example, the subscript of tTTX represents the TBI (T) transmit
(TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
Figure 14 shows the TBI transmit AC timing diagram.
tTTXR
tTTX
GTX_CLK
tTTXH
tTTXF
TXD[7:0]
TX_EN
TX_ER
tTTKHDX
Figure 14. TBI Transmit AC Timing Diagram
8.2.3.2
TBI Receive AC Timing Specifications
Table 30 provides the TBI receive AC timing specifications.
Table 30. TBI Receive AC Timing Specifications
At recommended operating conditions with LVDD/OVDD of 3.3 V 10%.
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
PMA_RX_CLK clock period
PMA_RX_CLK skew
RX_CLK duty cycle
tTRX
16.0
—
ns
ns
%
tSKTRX
7.5
40
8.5
60
tTRXH/tTRX
—
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
Freescale Semiconductor
28