Overview
NOTE
The information in this document is accurate for revision 3.x silicon and
later (in other words, for orderable part numbers ending in A or B). For
information on revision 1.1 silicon and earlier versions, see the MPC8349E
PowerQUICC II Pro Integrated Host Processor Hardware Specifications.
See Section 22.1, “Part Numbers Fully Addressed by This Document,” for
silicon revision level determination.
1 Overview
This section provides a high-level overview of the device features. Figure 1 shows the major functional
units within the MPC8349EA.
DDR/DDR2
DDR/DD
Memory Controller
Arbiter Bus
Monitor
R2
e300 Core
ROM
SDRAM
Local Bus Controller
32-KbyteL1 32-Kbyte
Programmable Interrupt
Controller
IRQs
Instruction
Cache
L1 Data
Cache
Coherent System Bus
Security Engine
64/32b PCI Controller
PCI1
PCI2
DMA
Serial Peripheral
Interface
SPI
Sequencer
SEQ
0/32b PCI Controller
DUART
Serial
DMA Controller
TSEC
I2C Interfaces
I2C
MII, GMII, TBI,
RTBI, RGMII
USB0
USB1
10/100/1Gb
USB Hi-Speed
Host Device
TSEC
MII, GMII, TBI,
RTBI, RGMII
10/100/1Gb
General Purpose I/O
GPIO
Figure 1. MPC8349EA Block Diagram
Major features of the device are as follows:
•
Embedded PowerPC e300 processor core; operates at up to 667 MHz
— High-performance, superscalar processor core
— Floating-point, integer, load/store, system register, and branch processing units
— 32-Kbyte instruction cache, 32-Kbyte data cache
— Lockable portion of L1 cache
— Dynamic power management
— Software-compatible with the other Freescale processor families that implement Power
Architecture technology
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
2
Freescale Semiconductor
FREESCALE [ Freescale ]
