FUNCTIONAL DEVICE OPERATION
OPERATING MODES
Figure 14. Memory Hold Circuit
EXITING FROM LOW POWER OFF MODES
When a Turn On event occurs, any switchers that are active through Low Power Off modes will stay in PFM mode at their
Standby voltage set points until the applicable time slot of the startup sequencer. At that point, the respective switcher is updated
for the PUMSx defined default state for mode and voltage. Subsequent closing of the power gate switches will be coordinated
by software to complete restoration of the full system power tree.
POWER GATING SPECIFICATIONS AND CONTROL
Table 37. Power Gating Characteristics
Parameter
Condition
Min
Typ
Max
Units
Output High
Output Low
5.0
5.40
5.70
100
100
1
V
mV
μs
μs
μA
V
Output Voltage VOUT
-
-
50
-
Turn-on Time (54), (55)
Turn Off Time
Enable to VOUT = VOUTMIN -250 mV
Disable to VOUT < 1.0 V
-
-
Average Bias Current
PWGTx Input Voltage
DC Load Current
t > 500 μs after Enable
-
1.0
-
5
NMOS drain voltage
0.6
-
2.0
100
1.0
At PWGTDRVx output
-
nA
nF
Load Capacitance (54)
Used as a condition for the other parameters
0.5
-
Notes
54. Larger capacitive loading values will lead to longer turn on times exceeding the given limits; smaller values will lead to larger ripple at
the output.
55. Input supply is assumed in the range of 3.0 < BP < 4.65 V; lower BP values may extend turn on time, and functionality not supported
for BP less than ~2.7 V.
A power gate driver pulled low may be thought of as power gating being active since this is the condition where a power source
is isolated (or power gated) from its loading on the other side of the switch. The power gate drive outputs are SPI controlled in
the active modes as shown in Table 38.
Table 38. Power Gate Drive State Control
Mode
PWGTDRV1
PWGTDRV2
Off
Low
Low
Low
Low
Cold Start
Warm Start
Low
Low
Watchdog, On, User Off Wait
SPI Controlled
Low
SPI Controlled
Low
User Off, Memory Hold, Internal Memory Hold Power Cut
13892
Analog Integrated Circuit Device Data
Freescale Semiconductor
69
FREESCALE [ Freescale ]
