FUNCTIONAL DEVICE OPERATION
OPERATING MODES
Table 34. Switcher Mode Control for Normal and Standby Operation
SWxMODE[3:0]
Normal mode(51)
Standby Mode(51)
1110
1111
PWMPS
PFM
PFM
PFM
Notes
51. STANDBY defined as logical AND of STANDBY and STANDBYSEC pin
In addition to controlling the operating mode in Standby, the voltage setting can be changed. The transition in voltage is
handled in a controlled slope manner, see Supplies, for details. Each switcher has an associated set of SPI bits for Standby mode
set points. By default the Standby settings are identical to the non-Standby settings, which are initially defined by PUMS
programming.
The actual operating mode of the switchers as a function of STANDBY pins is not reflected through the SPI. The SPI will read
back what is programmed in SWxMODE[3:0], not the actual state that may be altered as described previously.
Table 35 and Table 36 show the switcher mode control in the Low Power Off states. Note that a Low Power Off activated SWx
should use the Standby set point as programmed by SWxSTBY[4:0]. The activated switcher(s) will maintain settings for mode
and voltage until the next startup event. When the respective time slot of the startup sequencer is reached for a given switcher,
its mode and voltage settings will be updated the same as if starting out of the Off state (except that switchers active through a
Low Power Off mode will not be off when the startup sequencer is started).
Table 35. Switcher Control In Memory Hold
SWxMHMODE
Memory Hold Operational Mode (52)
0
1
Off
PFM
Notes
52. For Memory Hold mode, an activated SWx should use the Standby set point as programmed
by SWxSTBY[4:0].
Table 36. Switcher Control In User Off
SWxUOMODE
User Off Operational Mode (53)
0
1
Off
PFM
Notes
53. For User Off mode, an activated SWx should use the Standby set point as programmed by
SWxSTBY[4:0].
POWER GATING SYSTEM
The Low Power Off states are provided to allow faster system booting from two pseudo Off conditions: Memory Hold, which
keeps the external memory powered for self refresh, and User Off, which keeps the processor powered up for state retention.
For reduced current drain in Low Power Off states, parts of the system can benefit from power gating to isolate the minimum
essentials for such operational modes. It is also necessary to ensure that the power budget on backed up domains are within the
capabilities of switchers in PFM mode. An additional benefit of power gating peripheral loads during system startup is to enable
the processor core to complete booting, and begin running software before additional supplies or peripheral devices are powered.
This allows system software to bring up the additional supplies and close power gating switches in the most optimum order, to
avoid problems with supply sequencing or transient current surges. The power gating switch drivers and integrated control are
included for optimizing the system power tree.
The power gate drivers could be used for other general power gating as well. The text herein assumes the standard application
of PWGT1 for core supply power gating and PWGT2 for Memory Hold power gating.
USER OFF POWER GATING
User Off configuration maintains PFM mode switchers on both the processor and external memory power domains.
PWGTDRV1 is provided for power gating peripheral loads sharing the processor core supply domain(s) SW1, and/or SW2, and/
or SW3. In addition, PWGTDRV2 is provided support to power gate peripheral loads on the SW4 supply domain.
13892
Analog Integrated Circuit Device Data
Freescale Semiconductor
67
FREESCALE [ Freescale ]
