SPI BITMAP
Table 143. Register 31, Regulator Setting 1
Name
Reserved
Bit #
R/W
Reset
Default
Description
0
1
R
R
0
0
0
1
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
For future use
VVIDEO setting
VAUDIO setting
Reserved
VVIDEO0
VVIDEO1
VAUDIO0
VAUDIO1
VSD10
2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
RESETB
RESETB
RESETB
RESETB
RESETB
RESETB
RESETB
3
4
5
6
VSD11
7
VSD setting
VSD12
8
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
R
R
R
R
R
R
R
Not available
R
R
R
R
R
R
R
Table 144. Register 32, Regulator Mode 0
Name
Bit #
R/W
Reset
Default
Description
VGEN1EN
VGEN1STBY
VGEN1MODE
VIOHIEN
VIOHISTBY
Spare
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R
RESETB
RESETB
RESETB
NONE
0
0
0
*
VGEN1 enable
VGEN1 controlled by standby
VGEN1 operating mode
VIOHI enable
2
3
4
RESETB
RESETB
0
0
0
0
0
*
VIOHI controlled by standby
For future use
5
Unused
6
Not available
Unused
7
R
Not available
Unused
8
R
Not available
VDIGEN
9
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
NONE
RESETB
RESETB
NONE
VDIG enable
VDIGSTBY
Spare
10
11
12
13
14
15
16
17
18
19
20
0
0
*
VDIG controlled by standby
For future use
VGEN2EN
VGEN2STBY
VGEN2MODE
VPLLEN
VGEN2 enable
RESETB
RESETB
NONE
0
0
*
VGEN2 controlled by standby
VGEN2 operating mode
VPLL enable
VPLLSTBY
Spare
RESETB
RESETB
RESETB
RESETB
RESETB
0
0
0
0
0
VPLL controlled by standby
For future use
VUSB2EN
VUSB2STBY
Spare
VUSB2 enable
VUSB2 controlled by standby
For future use
13892
Analog Integrated Circuit Device Data
Freescale Semiconductor
139
FREESCALE [ Freescale ]
