BRUSHLESS DC MOTOR CONTROLLER
FSP33035
inputs. With Pin 22 in low (0) state, configuration is for 120° sensor electrical phasing inputs.
5. Valid 60° or 120° sensor combinations for corresponding valid top and bottom drive outputs.
6. Invalid sensor inputs with brake = 0; All top and bottom drives off, Fault low.
7. Invalid sensor inputs with brake = 1; All top drives off, all bottom drives on, Fault low.
8. Valid 60° or 120° sensor inputs with brake = 1; All top drives off, all bottom drives on, Fault high.
9. Valid sensor inputs with brake = 1 and enable = 0; All top drives off, all bottom drives on, Fault low.
10. Valid sensor inputs with brake = 0 and enable = 0; All top and bottom drives off, Fault low.
11. All bottom drives off, Fault low.
Error Amplifier
A high performance, fully compensated error amplifier with access to both inputs and output (Pins 11, 12, 13) is
provided to facilitate the implementation of closed loop motor speed control. The amplifier features a typical DC
voltage gain of 80 dB, 0.6 MHz gain bandwidth, and a wide input common mode voltage range that extends from
ground to Vref. In most open loop speed control applications, the amplifier is configured as a unity gain voltage
follower with the noninverting input connected to the speed set voltage source.
Oscillator
The frequency of the internal ramp oscillator is programmed by the values selected for timing components RT and
CT. Capacitor CT is charged from the Reference Output (Pin 8) through resistor RT and discharged by an internal
discharge transistor. The ramp peak and valley voltages are typically 4.1 V and 1.5 V respectively. To provide a good
compromise between audible noise and output switching efficiency, an oscillator frequency in the range of 20 to 30
kHz is recommended.
Pulse Width Modulator
The use of pulse width modulation provides an energy efficient method of controlling the motor speed by varying the
average voltage applied to each stator winding during the commutation sequence. As CT discharges, the oscillator
sets both latches, allowing conduction of the top and bottom drive outputs. The PWM comparator resets the upper
latch, terminating the bottom drive output conduction when the positive–going ramp of CT becomes greater than the
error amplifier output. The pulse width modulator timing diagram is shown in the Figure below. Pulse width
modulation for speed control appears only at the bottom drive outputs.
Pulse Width Modulator Timing Diagram Reference
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2007-3-16
FOSLINK [ FOSLINK SEMICONDUCTOR CO.,LTD ]
