F81866A
UART Data Terminal Ready. An active low signal
informs the modem or data set that controller is
ready to communicate.
DTR5#
O12
GPIO64
I/OOD12st, 5v
INst,5v
General Purpose IO.
Diskette change. This signal is active low at power
on and whenever the diskette is removed.
Data Set Ready. An active low signal indicates the
modem or data set is ready to establish a
communication link and transfer data to the UART.
DSKCHG#
21
3VCC
DSR5#
INst,5v
5.5 Parallel Port (LPT Port), & GPIO
Pin
Pin Name
Type
PWR
Description
Fan 3 tachometer input.
FANIN3
INst,5v
An active high input on this pin indicates that the
printer is selected. Refer to the description of the
parallel port for definition of this pin in ECP and EPP
mode.
102
3VCC
SLCT
GPIO70
PE
INst,5v
I/OOD12st, 5v
INst,5v
General purpose IO.
An active high input on this pin indicates that the
printer has detected the end of the paper. Refer to the
description of the parallel port for the definition of this
pin in ECP and EPP mode.
OOD12,5v
AOUT
Fan 3 control output. This pin provides PWM
duty-cycle output or a DAC voltage output.
103
3VCC
FANCTL3
Power on Strapping pin:
1: PWM mode.
PWM _DAC3
INst,5v
0: Default is DAC mode for FANCTL3 (internal pull
down 100kΩ ).
GPIO71
BUSY
I/OOD12st, 5v
General purpose IO.
An active high input indicates that the printer is not
ready to receive data. Refer to the description of the
parallel port for definition of this pin in ECP and EPP
mode.
104
105
3VCC
3VCC
INst,5v
GPIO72
ACK#
I/OOD12st, 5v
General purpose IO.
An active low input on this pin indicates that the
printer has received data and is ready to accept more
data. Refer to the description of the parallel port for
the definition of this pin in ECP and EPP mode.
General purpose IO.
INst,5v
GPIO73
SLIN#
I/OOD12st, 5v
I/OOD12st,5v
Output line for detection of printer selection. Refer to
the description of the parallel port for the definition of
this pin in ECP and EPP mode.
106
107
3VCC
3VCC
GPIO74
INIT#
I/OOD12st, 5v
I/OOD12st,5v
General purpose IO.
Output line for the printer initialization. Refer to the
description of the parallel port for the definition of this
20
Jan, 2012
V0. 12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
