F81866A
5.2 Clock
Pin
Pin Name
Type
PWR
Description
32
PCICLK
INst
3VCC 33MHz PCI clock input.
System clock input. According to the input frequency
14.318/24/48MHz (default 48MHz).
33
CLKIN
INst
3VCC
5.3 LPC Interface
Pin Name
Pin
Type
PWR
Description
Reset signal. It can connect to PCIRST# signal on the
host.
23
LRESET#
INst
3VCC
24
25
LDRQ#
O16
3VCC Encoded DMA Request signal.
3VCC Serial IRQ input/Output.
SERIRQ
I/O16st
Indicates start of a new cycle or termination of a broken
26
LFRAME#
INst
3VCC
cycle.
These signal lines communicate address, control, and
3VCC data information over the LPC bus between a host and
a peripheral.
27-30
32
LAD[0:3]
PCICLK
I/O16st
INst
3VCC 33MHz PCI clock input.
5.4 FDC, & GPIO
Pin
Pin Name
Type
PWR
Description
General Purpose IO.
I/OOD14st, 5v
GPIO50
Drive Density Select.
OD14
Set to 1 – High data rate.(500Kbps, 1Mbps)
Set to 0 – Low data rate. (250Kbps, 300Kbps)
UART Request To Send. An active low signal
informs the modem or data set that the controller is
ready to send data.
,5v
DENSEL#
RTS6#
9
3VCC
O14
I/OOD14st, 5v
General Purpose IO.
GPIO51
MOA#
Motor A On. When set to 0, this pin enables disk
drive 0. This is an open drain output.
UART Serial Input. Used to receive serial data
through the communication link.
OD14
,5v
10
11
12
3VCC
3VCC
3VCC
INst,5v
SIN6
GPIO52
I/OOD14st, 5v
General Purpose IO.
Drive Select A. When set to 0, this pin enables disk
drive A. This is an open drain output.
UART Serial Output. Used to transmit serial data
out to the communication link.
DRVA#
OD14
,5v
SOUT6
GPIO53
O14
I/OOD14st, 5v
General Purpose IO.
Write data. This logic low open drain writes
pre-compensation serial data to the selected FDD.
An open drain output.
WDATA#
DCD6#
OD14
,5v
INst,5v
Data Carrier Detect. An active low signal indicates
18
Jan, 2012
V0. 12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
