F81867
GPIO0 IRQ sharing mode:
00 : Sharing IRQ active low Level.
01 : Sharing IRQ active high edge.
10 : Sharing IRQ active high Level.
11 : Reserved.
LRESET#
1-0
GP0_IRQ_MODE
R/W
0
This bit is effective when IRQ is sharing with other device
(GP0_IRQ_SHARE is “1”).
7.7.4
GPIO0x Configuration Registers
Register Name
Register
0x[HEX]
Default Value
MSB
LSB
F0
GPIO0 Output Enable Register
GPIO0 Output Data Register
GPIO0 Pin Status Register
0
0
0
-
0
0
-
0
0
-
0
1
-
0
1
-
0
1
-
0
1
-
F1
F2
F3
F4
F5
F6
F7
F8
F9
0
-
GPIO0 Drive Enable Register
GPIO0 Output Mode 1 Register
GPIO0 Output Mode 2 Register
GPIO0 Pulse Width Select 1 Register
GPIO0 Pulse Width Select 2 Register
GPIO0 SMI Enable Register
GPIO0 SMI Status Register
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GPIO0 Output Enable Register ⎯ Index F0h
Bit
Name
R/W Reset Default
Description
0: GPIO07 is input.
1: GPIO07 is output.
7
GPIO07_OE
R/W 5VSB
R/W 5VSB
R/W 5VSB
R/W 5VSB
R/W 5VSB
R/W 5VSB
R/W 5VSB
0
0
0
0
0
0
0
0: GPIO06 is input.
1: GPIO06 is output.
6
5
4
3
2
1
GPIO06_OE
GPIO05_OE
GPIO04_OE
GPIO03_OE
GPIO02_OE
GPIO01_OE
0: GPIO05 is input.
1: GPIO05 is output.
0: GPIO04 is input.
1: GPIO04 is output.
0: GPIO03 is input.
1: GPIO03 is output.
0: GPIO02 is input.
1: GPIO02 is output.
0: GPIO01 is input.
1: GPIO01 is output.
145
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
