F81867
PECI, TSI, IBEX, Beta Register ⎯ Index 0Ah
Bit
Name
Defa
ult
Description
R/W
Reset
0: disable the T2 beta compensation.
7
6
BETA_EN2
BETA_EN1
R/W
R/W
5VSB
5VSB
0
0
1: enable the T2 beta compensation.
0: disable the T1 beta compensation.
1: enable the T1 beta compensation.
This bit is used to select AMD TSI or Intel IBEX when TSI_EN is set to 1.
5
4
INTEL_SEL
R/W
5VSB
1
0
0: Select AMD
1: Select Intel
MXM_MODE
R/W LRESET#
Reserved
PECI (VTT) voltage selection.
00: VTT is 1.23V
3-2
VTT_SEL
R/W
5VSB
0
01: VTT is 1.13V
10: VTT is 1.00V
11: VTT is 1.00V
Set this bit 1 to enable AMD TSI or Intel IBEX function
1
0
TSI_EN
R/W
R/W
5VSB
0
0
Set this bit 1 to enable Intel PECI function
PECI_EN
LRESET#
CUP Socket Select Register ⎯ Index 0Bh
Bit
Name
R/W Reset Default
Description
Select the Intel CPU socket number.
0000: no CPU presented. PECI host will use Ping () command to find the
CPU address.
0001: CPU is in socket 0, i.e. PECI address is 0x30.
0010: CPU is in socket 0, i.e. PECI address is 0x31.
0100: CPU is in socket 0, i.e. PECI address is 0x32.
1000: CPU is in socket 0, i.e. PECI address is 0x33.
7-4
CPU_SEL
R/W
5VSB
0
Others are reserved.
Reserved.
3-1
0
Reserved
-
-
0
0
If the CPU is selected as dual core. Set this register 1 to read the
temperature of domain1.
DOMAIN1_EN
R/W
5VSB
TCC Register ⎯ Index 0Ch
Bit
Name
R/W Reset Default
Description
TCC Activation Temperature.
When PECI is enabled, the absolute value of CPU temperature is
8’h55
calculated by the equation:
7-0
TCC_TEMP
R/W 5VSB
CPU_TEMP = TCC_TEMP + PECI Reading.
The range of this register is -128 ~ 127ºC.
48
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
