F81867
0: GPIO12 outputs 0 when in output mode.
1: GPIO12 outputs 1 when in output mode.
2
1
0
GPIO12_VAL
GPIO11_VAL
GPIO10_VAL
R/W 5VSB
R/W 5VSB
R/W 5VSB
1
1
1
0: GPIO11 outputs 0 when in output mode.
1: GPIO11 outputs 1 when in output mode.
0: GPIO10 outputs 0 when in output mode.
1: GPIO10 outputs 1 when in output mode.
GPIO1 Pin Status Register ⎯ Index E2h (This byte could be also read by base address + 7)
Bit
7
Name
R/W Reset Default
Description
The pin status of PECI/GPIO17.
GPIO17_IN
GPIO16_IN
GPIO15_IN
GPIO14_IN
GPIO13_IN
GPIO12_IN
GPIO11_IN
GPIO10_IN
R
R
R
R
R
R
R
R
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
6
The pin status of BEEP/GPIO16/SDA/CIRRX#.
The pin status of WDTRST#/GPIO15.
The pin status of GPIO14/AT_ATX_TRAP.
The pin status of SDA/GPIO13/IRRX.
The pin status of SCL/GPIO12/IRTX
The pin status of GPIO11/LED_VCC.
The pin status of GPIO10/LED_VSB.
5
4
3
2
1
0
GPIO1 Drive Enable Register ⎯ Index E3h
Name R/W Reset Default
Bit
Description
0: GPIO17 is open drain in output mode.
1: GPIO17 is push pull in output mode.
7
GPIO17_DRV_EN R/W 5VSB
GPIO16_DRV_EN R/W 5VSB
GPIO15_DRV_EN R/W 5VSB
GPIO14_DRV_EN R/W 5VSB
GPIO13_DRV_EN R/W 5VSB
GPIO12_DRV_EN R/W 5VSB
0
0
0
0
0
0
0: GPIO16 is open drain in output mode.
1: GPIO16 is push pull in output mode.
6
5
4
3
2
0: GPIO15 is open drain in output mode.
1: GPIO15 is push pull in output mode.
0: GPIO14 is open drain in output mode.
1: GPIO14 is push pull in output mode.
0: GPIO13 is open drain in output mode.
1: GPIO13 is push pull in output mode.
0: GPIO12 is open drain in output mode.
1: GPIO12 is push pull in output mode.
0: GPIO11 is open drain in output mode.
1: GPIO11 is push pull in output mode.
This bit is powered by VBAT.
1
0
GPIO11_DRV_EN R/W VBAT
GPIO10_DRV_EN R/W VBAT
0
0
0: GPIO10 is open drain in output mode.
1: GPIO10 is push pull in output mode.
This bit is powered by VBAT.
GPIO1 SMI Enable Register ⎯ Index E8h
Bit
Name
R/W Reset Default
Description
0: Disable SMI event.
7
GPIO17_SMI_EN
R/W 5VSB
R/W 5VSB
0
0
1: Enable SMI event via PME# or SIRQ if GPIO17_SMI_ST is set.
0: Disable SMI event.
6
GPIO16_SMI_EN
1: Enable SMI event via PME# or SIRQ if GPIO16_SMI_ST is set.
152
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
