F81866A
FAN3 SEGMENT 3 SPEED COUNT – Index CCh
Bit
Name
R/W Reset Default
Description
The meaning of this register is depending on the FAN3_MODE (CR96)
2’b00: The value that set in this byte is the relative expect fan speed % of
B2h
7-0
SEC3SPEED3
R/W
5VSB
(70%) the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM duty-cycle
in this temperature section.
FAN3 SEGMENT 4 SPEED COUNT – Index CDh
Bit
Name
R/W Reset Default
Description
The meaning of this register is depending on the FAN3_MODE (CR96)
2’b00: The value that set in this byte is the relative expect fan speed % of
the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM duty-cycle
in this temperature section.
99h
7-0
SEC4SPEED3
R/W
5VSB
(60%)
FAN3 SEGMENT 5 SPEED COUNT – Index CEh
Bit
Name
R/W Reset Default
Description
The meaning of this register is depending on the FAN3_MODE (CR96)
2’b00: The value that set in this byte is the relative expect fan speed % of
the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM duty-cycle
in this temperature section.
80h
7-0
SEC5SPEED3
R/W
5VSB
(50%)
FAN3 Temperature Mapping Select – Index CFh
Bit
Name
FAN3_TEMP_
SEL_DIG
R/W
Reset Default
Description
This bit companies with FAN3_TEMP_SEL select the temperature
source for controlling FAN3.
7
R/W
5VSB
0
This bit and FREQ_SEL_ADD3 are used to select FAN3 PWM
frequency. NEW_FREQ_SEL3 = { FREQ_SEL_ADD3,
FAN3_PWM_FREQ_SEL}
FAN3_PWM_
FREQ_SEL
6
R/W
00: 23.5 KHz
5VSB
0
01: 11.75 KHz
10: 5.875 KHz
11: 220 Hz
5
4
FAN3_UP_T_EN
FAN3_
R/W
R/W
Set 1 to force FAN3 to full speed if any temperature over its high limit.
5VSB
5VSB
0
1
Set 1 will enable the interpolation of the fan expect table.
INTERPOLATION_EN
84
Jan, 2012
V0. 12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
