F81866A
FAN PROGRAMMABLE DUTY-CYCLE/VOLTAGE LOADED AFTER POWER-ON ⎯ Index 9Eh
Bit
Name
R/W Reset Default
Description
This byte will be immediately loaded as Fan duty value after VDD is
powered on if it has been programmed before shut down.
7-0 PROG_DUTY_VAL R/W
66h
5VSB
Fan Fault Time Register ⎯ Index 9Fh
Bit
Name
R/W Reset Default
Description
7
FAN_PROG_SEL
R/W
0
0
Set this bit to “1” will enable accessing registers of other bank.
5VSB
Set this bit to monitor a slower fan.
Reserved
6
5
FAN_MNT_SEL
Reserved
R/W 5VSB
-
-
-
-
0: The Fan Duty is 100% and will be loaded immediately after VDD is
powered on if CR9E is not been programmed before shut down. (pull
down by external resistor)
4
FULL_DUTY_SEL
R/W 3VCC
1: The Fan Duty is 40% and will be loaded immediately after VDD is
powered on if CR9E is not been programmed before shut down. (pull up
by internal 47K Ω resistor).
This register is power on trap by DTR1#/FAN40_100.
This register determines the time of fan fault. The condition to cause fan
fault event is:
When PWM_Duty reaches FFh, if the fan speed count can’t reach the fan
expect count in time.
The unit of this register is 1 second. The default value is 11 seconds.
(Set to 0, means 1 seconds; Set to 1, means 2 seconds.
Set to 2, means 3 seconds. …. )
3-0
F_FAULT_TIME
R/W 5VSB
Ah
Another condition to cause fan fault event is fan stop and the PWM duty is
greater than the minimum duty programmed by the register index
9C-9Dh.
A. FAN1 Index A0h~AFh
Address
Attribute
Reset
3VCC
3VCC
Default
8’h0f
Description
FAN1 count reading (MSB). At the moment of reading this register,
the LSB will be latched. This will prevent from data updating when
reading. To read the fan count correctly, read MSB first and followed
read the LSB.
A0h
RO
A1h
RO
8’hff
FAN1 count reading (LSB).
73
Jan, 2012
V0. 12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
