F81866A
VIN3 under-voltage limit (V3_UVV_LIMIT). The unit is 8mv (This
39h
3Ah
R/W
R/W
VBAT
5VSB
96
byte is powered by VBAT)
FF
VIN1 OVP limit. The unit is 8mv (This byte is powered by VBAT)
6.4.2.5Fan Control Setting
FAN PME# Enable Register ⎯ Index 90h
Bit
Name
R/W Reset Default
Description
7-3
Reserved
R
0
Reserved
-
A one enables the corresponding interrupt status bit for PME# interrupt
Set this bit 1 to enable PME# function for Fan3.
2
1
0
EN_FAN3_PME
EN_FAN2_PME
EN_FAN1_PME
R/W 5VSB
R/W 5VSB
R/W 5VSB
0
A one enables the corresponding interrupt status bit for PME# interrupt.
Set this bit 1 to enable PME# function for Fan2.
0
0
A one enables the corresponding interrupt status bit for PME# interrupt.
Set this bit 1 to enable PME# function for Fan1.
FAN Interrupt Status Register ⎯ Index 91h
Bit
Name
R/W Reset Default
Description
7-3
Reserved
R
0
Reserved
-
This bit is set when the fan3 count exceeds the count limit. Write 1 to
clear this bit, write 0 will be ignored.
2
1
0
FAN3_STS
FAN2_STS
FAN1_STS
R/W 3VCC
R/W 3VCC
R/W 3VCC
--
This bit is set when the fan2 count exceeds the count limit. Write 1 to
clear this bit, write 0 will be ignored.
--
--
This bit is set when the fan1 count exceeds the count limit. Write 1 to
clear this bit, write 0 will be ignored.
FAN Real Time Status Register ⎯ Index 92h
Bit
Name
R/W Reset Default
Description
7-3
Reserved
--
R
0
Reserved
-
This bit set to high mean that fan3 count can’t meet the expected count
over than SMI time (CR9F) or when duty not zero but fan stop over then 3
sec.
2
FAN3_EXC
3VCC
--
This bit set to high mean that fan2 count can’t meet expect count over
than SMI time (CR9F) or when duty not zero but fan stop over then 3 sec.
This bit set to high mean that fan1 count can’t meet expect count over
than SMI time (CR9F) or when duty not zero but fan stop over then 3 sec.
1
0
FAN2_EXC
FAN1_EXC
R
R
3VCC
3VCC
--
--
65
Jan, 2012
V0. 12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
