F81218
5
4
3
2
1
0
PME_ST_EDGE1[5]
PME_ST_EDGE1[4]
PME_ST_EDGE1[3]
PME_ST_EDGE1[2]
PME_ST_EDGE1[1]
PME_ST_EDGE1[0]
R/W
R/W
R/W
R/W
R/W
R/W
0 : No transition at GP25
1 : A high to low transition at GP25 in input mode.
0 : No transition at GP24
1 : A high to low transition at GP24 in input mode.
0 : No transition at GP23
1 : A high to low transition at GP23 in input mode.
0 : No transition at GP22
1 : A high to low transition at GP22 in input mode.
0 : No transition at GP21
1 : A high to low transition at GP21 in input mode.
0 : No transition at GP20
1 : A high to low transition at GP20 in input mode.
6.11.12
PME Edge Status 2 Register – index FBh
Power on default = 0x00h
Bit Name
Reserved
R/W
R/W
R/W
Description
7
Return 0 when read.
6
5
4
3
2
1
0
PME_ST_EDGE2[6]
PME_ST_EDGE2[5]
PME_ST_EDGE2[4]
PME_ST_EDGE2[3]
PME_ST_EDGE2[2]
PME_ST_EDGE2[1]
PME_ST_EDGE2[0]
0 : No transition at GP16
1 : A high to low transition at GP16 in input mode.
0 : No transition at GP15
R/W
R/W
R/W
R/W
R/W
R/W
1 : A high to low transition at GP15 in input mode.
0 : No transition at GP14
1 : A high to low transition at GP14 in input mode.
0 : No transition at GP13
1 : A high to low transition at GP13 in input mode.
0 : No transition at GP12
1 : A high to low transition at GP12 in input mode.
0 : No transition at GP11
1 : A high to low transition at GP11 in input mode.
0 : No transition at GP10
1 : A high to low transition at GP10 in input mode.
6.11.13 PME Edge Status 3 Register – index FCh
Power on default = 0x00h
-49-
August, 2007
V0.33P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
