Default is disable.
0
EN_GP10EDGE
R/W
VSB3V Enable GPIO10 Edge Detector. If set to 1, enable GPIO10 edge detection.
Default is disable.
7.19 Edge Detector Status Register – Index 0x19
Power-on default [7:0] =0000_0000b
Bit
Name
STS_GP17ED
GE
R/W
PWR
Description
7
RW
VSB3V Indicate GPIO17 Edge Status. If set to 1, the edge of GPIO17 has occurred.
Writing 1 will clear this bit to 0. Writing 0 is invalid.
6
5
4
3
2
STS_GP16ED
GE
RW
RW
RW
RW
RW
VSB3V Indicate GPIO16 Edge Status. If set to 1, the edge of GPIO16 has occurred.
Writing 1 will clear this bit to 0. Writing 0 is invalid.
STS_GP15ED
GE
VSB3V Indicate GPIO15 Edge Status. If set to 1, the edge of GPIO15 has occurred.
Writing 1 will clear this bit to 0. Writing 0 is invalid.
STS_GP14ED
GE
VSB3V Indicate GPIO14 Edge Status. If set to 1, the edge of GPIO14 has occurred.
Writing 1 will clear this bit to 0. Writing 0 is invalid.
STS_GP13ED
GE
VSB3V Indicate GPIO13 Edge Status. If set to 1, the edge of GPIO13 has occurred.
Writing 1 will clear this bit to 0. Writing 0 is invalid.
STS_GP12ED
GE
VSB3V Indicate GPIO12 Edge Status. If set to 1, the edge of GPIO12 has occurred.
Writing 1 will clear this bit to 0. Writing 0 is invalid. If this bit serves as
IRQ/SMI#, this bit has no effect.
1
0
STS_GP11ED
GE
RW
RW
VSB3V Indicate GPIO11 Edge Status. If set to 1, the edge of GPIO11 has occurred.
Writing 1 will clear this bit to 0. Writing 0 is invalid.
STS_GP10ED
GE
VSB3V Indicate GPIO10 Edge Status. If set to 1, the edge of GPIO10 has occurred.
Writing 1 will clear this bit to 0. Writing 0 is invalid.
7.20 IRQ or SMI# Enable Register – Index 0x1A
Power-on default [7:0] =0000_0000b
Bit
Name
R/W
PWR
Description
7
EN_GP17IRQ
R/W
VSB3V Enable GPIO17 IRQ or SMI# Generation. If this bit set to 1, enable GPIO17
to generate IRQ or SMI#.
6
5
4
EN_GP16IRQ
EN_GP15IRQ
EN_GP14IRQ
R/W
R/W
R/W
VSB3V Enable GPIO16 IRQ or SMI# Generation. If this bit set to 1, enable GPIO16
to generate IRQ or SMI#.
VSB3V Enable GPIO15 IRQ or SMI# Generation. If this bit set to 1, enable GPIO15
to generate IRQ or SMI#.
VSB3V Enable GPIO14 IRQ or SMI# Generation. If this bit set to 1, enable GPIO14
to generate IRQ or SMI#.
- 21 -
July, 2007
V0.24P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
