high pulse. Default low pulse. The pulse width is defined in CR14.
VSB3V GPIO 16 Pulse inversed. If the pulse inverse is selected, the output pulse is
high pulse. Default low pulse. The pulse width is defined in CR14.
6
5
4
3
2
GP16_PULSINV
GP15_PULSINV
GP14_PULSINV
GP13_PULSINV
GP12_PULSINV
R/W
R/W
R/W
R/W
R/W
VSB3V GPIO15 Pulse inversed. If the pulse inverse is selected, the output pulse is
high pulse. Default low pulse. The pulse width is defined in CR14.
VSB3V GPIO14 Pulse inversed. If the pulse inverse is selected, the output pulse is
high pulse. Default low pulse. The pulse width is defined in CR14.
VSB3V GPIO13 Pulse inversed. If the pulse inverse is selected, the output pulse is
high pulse. Default low pulse. The pulse width is defined in CR14.
VSB3V GPIO12 Pulse inversed. If the pulse inverse is selected, the output pulse is
high pulse. Default low pulse. The pulse width is defined in CR14. If this pin
services as IRQ/SMI#, this bit has no effect.
1
0
GP11_PULSINV
GP10_PULSINV
R/W
R/W
VSB3V GPIO 11 Pulse inversed. If the pulse inverse is selected, the output pulse is
high pulse. Default low pulse. The pulse width is defined in CR14.
VSB3V GPIO10 Pulse inversed. If the pulse inverse is selected, the output pulse is
high pulse. Default low pulse. The pulse width is defined in CR14.
7.18 Edge Detector Enable Register – Index 0x18
Power-on default [7:0] =0000_0000b
Bit
Name
R/W
PWR
Description
7
EN_GP17EDGE
R/W
VSB3V Enable GPIO17 Edge Detector. If set to 1, enable GPIO17 edge detection.
Default is disable.
6
5
4
3
2
1
EN_GP16EDGE
EN_GP15EDGE
EN_GP14EDGE
EN_GP13EDGE
EN_GP12EDGE
EN_GP11EDGE
R/W
R/W
R/W
R/W
R/W
R/W
VSB3V Enable GPIO16 Edge Detector. If set to 1, enable GPIO16 edge detection.
Default is disable.
VSB3V Enable GPIO15 Edge Detector. If set to 1, enable GPIO15 edge detection.
Default is disable.
VSB3V Enable GPIO14 Edge Detector. If set to 1, enable GPIO14 edge detection.
Default is disable.
VSB3V Enable GPIO13 Edge Detector. If set to 1, enable GPIO13 edge detection.
Default is disable.
VSB3V Enable GPIO12 Edge Detector. If set to 1, enable GPIO12 edge detection.
Default is disable. If this bit serves as IRQ/SMI#, this bit has no effect.
VSB3V Enable GPIO11 Edge Detector. If set to 1, enable GPIO11 edge detection.
- 20 -
July, 2007
V0.24P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
