F75113
Set 1 to enable clear function of GPIO2X register by WDT1
resetout. When WatchDog timer1 count down to zero, the WDT1
resetout will clear GP_OCTRL(30h), GP_ODATA(31h),
GP_OMODE(33h), GP_PLSWD(34h), GP_RESON(35h),
GP_ENDB(36h), GP_PLSINV(37h), EN_GPEDGE(38h),
STS_GPEDGE(39h), EN_GPSMI(3Ah), EN_GP_OBUF(3Bh),
DB_TIME_SEL(3Ch) register.
2
1
0
WDT1_CGP2_EN R/W
WDT1_CGP1_EN R/W
WDT1_CGP0_EN R/W
0
0
0
Set 1 to enable clear function of GPIO1X register by WDT1
resetout. When WatchDog timer1 count down to zero, the WDT1
resetout will clear GP_OCTRL(20h), GP_ODATA(21h),
GP_OMODE(23h), GP_PLSWD(24h), GP_RESON(25h),
GP_ENDB(26h), GP_PLSINV(27h), EN_GPEDGE(28h),
STS_GPEDGE(29h), EN_GPSMI(2Ah), EN_GP_OBUF(2Bh),
DB_TIME_SEL(2Ch) register.
Set 1 to enable clear function of GPIO0X register by WDT1
resetout. When WatchDog timer1 count down to zero, the WDT1
resetout will clear GP_OCTRL(10h), GP_ODATA(11h),
GP_OMODE(13h), GP_PLSWD(14h), GP_RESON(15h),
GP_ENDB(16h), GP_PLSINV(17h), EN_GPEDGE(18h),
STS_GPEDGE(19h), EN_GPSMI(1Ah), EN_GP_OBUF(1Bh),
DB_TIME_SEL(1Ch) register.
8.2.23 WDT2 Reset GPIO Function Enable Register ⎯ Index 58h
Bit
7
Name
R/W Default
Description
Reserved
Reserved
Reserved
-
-
-
-
-
-
Reserved
Reserved
Reserved
6
5
Set 1 to enable clear function of GPIO4X register by WDT2
resetout. When WatchDog timer2 count down to zero, the WDT2
resetout will clear GP_OCTRL(70h), GP_ODATA(71h),
GP_OMODE(73h), GP_PLSWD(74h), GP_RESON(75h),
GP_ENDB(76h), GP_PLSINV(77h), EN_GPEDGE(78h),
STS_GPEDGE(79h), EN_GPSMI(7Ah), EN_GP_OBUF(7Bh),
DB_TIME_SEL(7Ch) register.
4
WDT2_CGP4_EN R/W
0
- 64 -
Dec,2011
V0.13P