F75113
Indicate GPIO11 Edge Status. If set to 1, the edge of GPIO11
1
0
STS_GP11EDGE
STS_GP10EDGE
R
R
-
-
has occurred. Write 1 to clear this bit. Writing 0 is invalid.
Indicate GPIO10 Edge Status. If set to 1, the edge of GPIO10
has occurred. Write 1 to clear this bit. Writing 0 is invalid.
8.2.37 GPIO1X SMI Enable Register ⎯ Index 2Ah
Bit
Name
R/W Default
Description
Enable GPIO17 SMI Generation. If this bit set to 1, enable
GPIO17 to generate SMI.
7
EN_GP17SMI
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Enable GPIO16 SMI Generation. If this bit set to 1, enable
GPIO16 to generate SMI.
6
5
4
3
2
1
0
EN_GP16SMI
EN_GP15SMI
EN_GP14SMI
EN_GP13SMI
EN_GP12SMI
EN_GP11SMI
EN_GP10SMI
Enable GPIO15 SMI Generation. If this bit set to 1, enable
GPIO15 to generate SMI.
Enable GPIO14 SMI Generation. If this bit set to 1, enable
GPIO14 to generate SMI.
Enable GPIO13 SMI Generation. If this bit set to 1, enable
GPIO13 to generate SMI.
Enable GPIO12 SMI Generation. If this bit set to 1, enable
GPIO12 to generate SMI.
Enable GPIO11 SMI Generation. If this bit set to 1, enable
GPIO11 to generate SMI.
Enable GPIO10 SMI Generation. If this bit set to 1, enable
GPIO10 to generate SMI.
8.2.38 GPIO1X Output Driving Enable Register ⎯ Index 2Bh
Bit
Name
R/W Default
Description
Enable GPIO17 drive high buffer. If this bit is set to 0, the pin
GPIO17 will be I/OD pin, if set to 1 the pin GPIO17 is I/O pin.
7
EN_GP17_OBUF R/W
EN_GP16_OBUF R/W
EN_GP15_OBUF R/W
0
0
0
Enable GPIO16 drive high buffer. If this bit is set to 0, the pin
GPIO16 will be I/OD pin, if set to 1 the pin GPIO16 is I/O pin.
6
5
Enable GPIO15 drive high buffer. If this bit is set to 0, the pin
GPIO15 will be I/OD pin, if set to 1 the pin GPIO15 is I/O pin.
- 41 -
Dec,2011
V0.13P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
