F71872
Clock Select Register Index F0h
Bit
Name
R/W Default
Description
7-6 SELCLK_KBC
R/W
10
00: select 6MHz clock as KBC clock input.
01: select 8MHz clock as KBC clock input.
10: select 12MHz clock as KBC clock input (default).
11: select 16MHz clock as KBC clock input.
5-2 Reserved
-
-
Reserved.
1
0
GA20_EN
HKBRST
R/W
1
0: GATE20# software control.
1: GATE20# hardware speed up.
R/W
1
0: KBRST# software control.
1: KBRST# hardware speed up.
KBC Test Mode Register Index F1h
Bit
Name
R/W Default
Description
7-0 TEST_MODE_KBC
-
00h Reserved for Fintek test mode only.
7.7.3 Device Registers
7.7.3.1 Status Register
The status register is an 8 bits register at I/O address 64h that provides information about the status of the KBC
Bit
Name
Parity error
R/W Default
Description
7
R
R
R
R
R
0
0
0
0
0
0:odd parity
1:even parity
6
5
4
3
Time out
0:no time out error
1:time out error
Auxiliary device
OBF
0: Auxiliary output buffer empty
1: Auxiliary output buffer full
Inhinit
0:keyboard is inhibited
1: keyboard is not inhibited
Command/data
0:data byte
1:command byte
R
R
2
1
SYSTEM_FLAG
IBF
0
0
This bit is set or clear by command byte of KBC
0:input buffer empty
1: input buffer full
R
0
OBF
0
0:output buffer empty
1: output buffer full
90
July, 2007
V0.28P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
