F71862
ECP Configuration Register A Base + 400h
Bit
Name
R/W Default
Description
7
IRQ_MODE
R
R
0
0: interrupt is ISA pulse.
1: interrupt is ISA level.
Only valid in ECP and ECP_MODE is 111b.
6-4 IMPID
001 000: the design is 16-bit implementation.
001: the design is 8-bit implementation (default).
010: the design is 32-bit implementation.
011-111: Reserved.
Only valid in ECP and ECP_MODE is 111b.
3
2
Reserved
-
-
Reserved.
BYTETRAN_N
R
1
0: when transmitting there is 1 byte waiting in the transceiver that does not
affect the FIFO full condition.
1: when transmitting the state of the full bit includes the byte being transmitted.
Only valid in ECP and ECP_MODE is 111b.
1-0 Reserved
R
00
Return 00 when read.
Only valid in ECP and ECP_MODE is 111b.
ECP Configuration Register B Base + 401h
Bit
Name
R/W Default
Description
7
COMP
R
0
1
0: only send uncompressed data.
1: compress data before sending.
Only valid in ECP and ECP_MODE is 111b.
6
Reserved
R
R
Reserved. Return 1 when read.
Only valid in ECP and ECP_MODE is 111b.
5-3 ECP_IRQ_CH
001 000: the interrupt selected with jumper.
001: select IRQ 7 (default).
010: select IRQ 9.
011: select IRQ 10.
100: select IRQ 11.
101: select IRQ 14.
110: select IRQ 15.
111: select IRQ 5.
Only valid in ECP and ECP_MODE is 111b.
2-0 ECP_DMA_CH
R
011 Return the DMA channel of ECP parallel port.
Only valid in ECP and ECP_MODE is 111b.
Extended Control Register Base + 402h
Bit Name R/W Default
Description
38
July, 2008
V.28P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
