F71862
4
SOFTPD_HM
R/W
0
Power down the Hardware Monitor device. This will stop the Hardware Monitor
clock.
3
2
1
0
SOFTPD_PRT
SOFTPD_UR2
SOFTPD_UR1
SOFTPD_FDC
R/W
R/W
R/W
R/W
0
0
0
0
Power down the Parallel Port device. This will stop the Parallel Port clock.
Power down the UART 2 device. This will stop the UART 2 clock.
Power down the UART 1 device. This will stop the UART 1 clock.
Power down the FDC device. This will stop the FDC clock.
8.1.8
Bit
UART IRQ Sharing Register Index 26h
Name
R/W Default
Description
7
CLK24M_SEL
R/W
0
0: CLKIN is 48MHz
1: CLKIN is 24MHz
6-2 Reserved
-
-
Reserved.
1
IRQ_MODE
R/W
0
0: PCI IRQ sharing mode (low level).
1: ISA IRQ sharing mode (low pulse).
o
IRQ_SHAR
R/W
0
0: disable IRQ sharing of two UART devices.
1: enable IRQ sharing of two UART devices.
8.1.9
Bit
ROM Address Select Register Index 27h
Name
R/W Default
Description
7
6
ROM_WR_EN
R/W
R/W
0
-
0: disable ROM writing
1: enable ROM writing
SPI_EN
0: SPI disable
1: SPI enable
This register is power on trapped by SOUT2/SPI_TRAP. Pull down to enable
SPI.
5
4
SPI_BIOS_EN
PORT_4E_EN
R/W
R/W
-
-
0: use SPI bridge for BIOS
1: Reserved
This register is power on trapped by DTR2#/FWH_TRAP. Pull down to enable
SPI bridge for BIOS.
0: The configuration register port is 2E/2F.
1: The configuration register port is 4E/4F.
This register is power on trapped by SOUT1/ Config4E_2E. Pull down to select
port 2E/2F.
3
2
SEG_000E_EN
SEG_FFF8_EN
R/W
R/W
-
-
0: disable address 0x000E0000 – 0x000EFFFF decode
1: enable address 0x000E0000 – 0x000EFFFF decode
This register is power on trapped by SOUT2/SPI_DIS. Pull down to enable.
0: disable address 0xFFF80000
0x000FFFFF decode
–
0xFFFFFFFF and 0x000F0000
–
–
1: enable address 0xFFF80000
0x000FFFFF decode
–
0xFFFFFFFF and 0x000F0000
This register is power on trapped by SOUT2/SPI_DIS. Pull down to enable.
73
July, 2008
V.28P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
