F71862
resumed.
VBAT
VSB
RSM RST#
S3#
PS_ON#
PSIN#
PSOUT#
VCC3V
DEFAULT TIM ING
Alwaysoff
VBAT
VSB
RSM RST#
S3#
PS_ON#
PSIN#
PSOUT#
VCC3V
ALwaysON TIM ING
PCI Reset and PWROK Signals
The F71862 supports 3 output buffers for 3 reset signals. If the register RSTCON_EN is set
to 1, the pin RSTCON# will infect PCIRST1# ~ PCIRST3# outcome. Then, the result of PCIRST#
outcome will be affected by conditions as below:
PCIRST1# Æ Output buffer of RSTCON# and LRESET#.
PCIRST2# Æ Output buffer of RSTCON# and LRESET#.
PCIRST3# Æ Output buffer of RSTCON# and LRESET#.
64
July, 2008
V.28P